[External] Re: Current status of RISC-V init_cache_level()

[yunhui cui]

Hi Conor,

On Thu, Jan 18, 2024 at 9:25 PM Conor Dooley <conor at kernel.org> wrote:
>
> On Thu, Jan 18, 2024 at 07:40:42PM +0800, yunhui cui wrote:
> > Hi Conor,
>
> Firstly, please don't send me off-list mails about such things
> and instead, please reply to the relevant threads on lkml.
>
> > There is no cache subdirectory in /sys/devices/system/cpu/cpu0/, so
> > lscpu cannot see the cache information. I found that the reason is
> > that init_cache_level() is not implemented on RISC-V.
>
> What version of the kernel are you using? I had a brief check to make
> sure something had not gone awry recently and I could see them on my
> system. What do the cpu nodes in your DT look like, assuming you are
> on a DT system?

The results of top commit using linux-next on qemu, It should not
matter if it is combined with DT, because the following function flow
directly fails.
cacheinfo_sysfs_init()...init_cache_level()
int __weak init_cache_level(unsigned int cpu)
{
return -ENOENT;
}
Is it necessary to implement an init_cache_level() on RISC-V like other arches?

BTW, Does cat /proc/cpuinfo expose cache-related information, such as
cache size?

Thanks,
Yunhui