Current status of RISC-V init_cache_level()

[Conor Dooley]

On Thu, Jan 18, 2024 at 07:40:42PM +0800, yunhui cui wrote:
> Hi Conor,

Firstly, please don't send me off-list mails about such things
and instead, please reply to the relevant threads on lkml.

> There is no cache subdirectory in /sys/devices/system/cpu/cpu0/, so
> lscpu cannot see the cache information. I found that the reason is
> that init_cache_level() is not implemented on RISC-V.

What version of the kernel are you using? I had a brief check to make
sure something had not gone awry recently and I could see them on my
system. What do the cpu nodes in your DT look like, assuming you are
on a DT system?

> The history of the patch can be found by searching, as follows:
> https://www.spinics.net/lists/arm-kernel/msg1024976.html

I don't follow. This was the first iteration of a series that was merged
about a year ago and it moved the risc-v specific cache level
initialisation code to a common location and re-uses it for arm64.

> How is the progress of this patch?

A later iteration has been merged. Please use lore.kernel.org instead of
spinics - you can search for patchsets more easily (eg by filename) and
you could see it was merged in a later form.

Thanks,
Conor.
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