[PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea at tuxon.dev>
> Sent: Thursday, February 8, 2024 12:43 PM
> Subject: [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain
> IDs
> 
> From: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
> 
> Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj at bp.renesas.com>
> ---
>  include/dt-bindings/clock/r9a07g043-cpg.h | 48 +++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-
> bindings/clock/r9a07g043-cpg.h
> index 77cde8effdc7..eabfeec7ac37 100644
> --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> @@ -200,5 +200,53 @@
>  #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
>  #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
> 
> +/* Power domain IDs. */
> +#define R9A07G043_PD_ALWAYS_ON		0
> +#define R9A07G043_PD_GIC		1
> +#define R9A07G043_PD_IA55		2
> +#define R9A07G043_PD_MHU		3
> +#define R9A07G043_PD_CORESIGHT		4
> +#define R9A07G043_PD_SYC		5
> +#define R9A07G043_PD_DMAC		6
> +#define R9A07G043_PD_GTM0		7
> +#define R9A07G043_PD_GTM1		8
> +#define R9A07G043_PD_GTM2		9
> +#define R9A07G043_PD_MTU		10
> +#define R9A07G043_PD_POE3		11
> +#define R9A07G043_PD_WDT0		12
> +#define R9A07G043_PD_SPI		13
> +#define R9A07G043_PD_SDHI0		14
> +#define R9A07G043_PD_SDHI1		15
> +#define R9A07G043_PD_ISU		16
> +#define R9A07G043_PD_CRU		17
> +#define R9A07G043_PD_LCDC		18
> +#define R9A07G043_PD_SSI0		19
> +#define R9A07G043_PD_SSI1		20
> +#define R9A07G043_PD_SSI2		21
> +#define R9A07G043_PD_SSI3		22
> +#define R9A07G043_PD_SRC		23
> +#define R9A07G043_PD_USB0		24
> +#define R9A07G043_PD_USB1		25
> +#define R9A07G043_PD_USB_PHY		26
> +#define R9A07G043_PD_ETHER0		27
> +#define R9A07G043_PD_ETHER1		28
> +#define R9A07G043_PD_I2C0		29
> +#define R9A07G043_PD_I2C1		30
> +#define R9A07G043_PD_I2C2		31
> +#define R9A07G043_PD_I2C3		32
> +#define R9A07G043_PD_SCIF0		33
> +#define R9A07G043_PD_SCIF1		34
> +#define R9A07G043_PD_SCIF2		35
> +#define R9A07G043_PD_SCIF3		36
> +#define R9A07G043_PD_SCIF4		37
> +#define R9A07G043_PD_SCI0		38
> +#define R9A07G043_PD_SCI1		39
> +#define R9A07G043_PD_IRDA		40
> +#define R9A07G043_PD_RSPI0		41
> +#define R9A07G043_PD_RSPI1		42
> +#define R9A07G043_PD_RSPI2		43
> +#define R9A07G043_PD_CANFD		44
> +#define R9A07G043_PD_ADC		45
> +#define R9A07G043_PD_TSU		46

Not sure from "Table 42.3 Registers for Module Standby Mode"

Power domain ID has to be based on CPG_BUS_***_MSTOP or CPG_CLKON_***
As former reduces number of IDs??

Cheers,
Biju