Some feedbacks on RISC-V IOMMU driver

[Jessica Clarke]

On 19 Aug 2024, at 04:56, Xu Lu <luxu.kernel at bytedance.com> wrote:
> 
> Hi Tomasz,
> 
> Thanks for your brilliant job on RISC-V IOMMU driver. It helps us a
> lot for what we are doing. Below is our feedback on the existing
> implementation[1].
> 
> 1) Some IOMMU HW may only support 32-bit granularity access on its
> control registers (even when the register is 8 byte length). Maybe it
> is better to provide a 32-bit access method for 8 byte length
> registers like what opensbi does on ACLINT MTIME register.

That OpenSBI has to access MTIME piecewise is a workaround for a vendor
not implementing what the spec clearly intended, even if it wasn’t
explicitly stated (but is now, in response to that). Repeating that
situation would be a pitiful mistake.

The current IOMMU spec draft very clearly states:

  "Registers that are 64-bit wide may be accessed using either a 32-bit
   or a 64-bit access.”

Jess

> 2) In the IOMMU fault queue handling procedure, I wonder whether it is
> better to clear the fqmf/fqof bit first, and then clear the ipsr.fip
> bit. Otherwise the ipsr.fip can not be cleared and a redundant
> interrupt will be signaled.
> 
> Best regards!
> Xu Lu
> 
> [1] https://lore.kernel.org/all/cover.1718388908.git.tjeznach@rivosinc.com/
> 
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