Some feedbacks on RISC-V IOMMU driver

[Xu Lu]

Hi Tomasz,

Thanks for your brilliant job on RISC-V IOMMU driver. It helps us a
lot for what we are doing. Below is our feedback on the existing
implementation[1].

1) Some IOMMU HW may only support 32-bit granularity access on its
control registers (even when the register is 8 byte length). Maybe it
is better to provide a 32-bit access method for 8 byte length
registers like what opensbi does on ACLINT MTIME register.

2) In the IOMMU fault queue handling procedure, I wonder whether it is
better to clear the fqmf/fqof bit first, and then clear the ipsr.fip
bit. Otherwise the ipsr.fip can not be cleared and a redundant
interrupt will be signaled.

Best regards!
Xu Lu

[1] https://lore.kernel.org/all/cover.1718388908.git.tjeznach@rivosinc.com/