[PATCH v4 3/3] riscv: dts: sophgo: Add SARADC description for Sophgo CV18XX

[Chen Wang]

On 2024/8/13 9:50, Inochi Amaoto wrote:
> On Tue, Aug 13, 2024 at 09:45:53AM GMT, Chen Wang wrote:
>> On 2024/8/12 23:00, Thomas Bonnefille wrote:
>>> Adds SARADC nodes for the common Successive Approximation Analog to
>>> Digital Converter used in Sophgo CV18xx series SoC.
>>> This patch adds two nodes for the two controllers the board, one in
>>> the Active domain and the other in the No-Die domain.
>> Where is the node for the No-die domain?
> I have suggested Thomas not add the node for the RTC domain.
> It is not clear that which clock is used for the RTC domain,
> it will good to add this node after the RTC is implemented.
OK，so please update the commit message and mention this.
>
>>> Signed-off-by: Thomas Bonnefille <thomas.bonnefille at bootlin.com>
>>> ---
>>>    arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 20 ++++++++++++++++++++
>>>    1 file changed, 20 insertions(+)
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> index 891932ae470f..71a2618852fa 100644
>>> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>>> @@ -133,6 +133,26 @@ portd: gpio-controller at 0 {
>>>    			};
>>>    		};
>>> +		saradc: adc at 30f0000 {
>>> +			compatible = "sophgo,cv1800b-saradc";
>>> +			reg = <0x030f0000 0x1000>;
>>> +			clocks = <&clk CLK_SARADC>;
>>> +			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <0>;
>>> +			status = "disabled";
>>> +
>>> +			channel at 0 {
>>> +				reg = <0>;
>>> +			};
>>> +			channel at 1 {
>>> +				reg = <1>;
>>> +			};
>>> +			channel at 2 {
>>> +				reg = <2>;
>>> +			};
>>> +		};
>>> +
>>>    		i2c0: i2c at 4000000 {
>>>    			compatible = "snps,designware-i2c";
>>>    			reg = <0x04000000 0x10000>;
>>>