[RFC v1 1/6] riscv: dts: microchip: convert isa detection to new properties

[Chen Wang]

在 2023/9/21 17:57, Conor Dooley 写道:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> Convert the PolarFire SoC devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>   arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index 104504352e99..b1f873d9246c 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -22,6 +22,9 @@ cpu0: cpu at 0 {
>   			i-cache-size = <16384>;
>   			reg = <0>;
>   			riscv,isa = "rv64imac";
> +			riscv,base-isa = "rv64i";
should be "isa-base". This applies everywhere.
> +			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
> +					       "zihpm";
>   			clocks = <&clkcfg CLK_CPU>;
>   			status = "disabled";
>   
> @@ -48,6 +51,9 @@ cpu1: cpu at 1 {
>   			mmu-type = "riscv,sv39";
>   			reg = <1>;
>   			riscv,isa = "rv64imafdc";
> +			riscv,base-isa = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";
>   			clocks = <&clkcfg CLK_CPU>;
>   			tlb-split;
>   			next-level-cache = <&cctrllr>;
> @@ -76,6 +82,9 @@ cpu2: cpu at 2 {
>   			mmu-type = "riscv,sv39";
>   			reg = <2>;
>   			riscv,isa = "rv64imafdc";
> +			riscv,base-isa = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";
>   			clocks = <&clkcfg CLK_CPU>;
>   			tlb-split;
>   			next-level-cache = <&cctrllr>;
> @@ -104,6 +113,9 @@ cpu3: cpu at 3 {
>   			mmu-type = "riscv,sv39";
>   			reg = <3>;
>   			riscv,isa = "rv64imafdc";
> +			riscv,base-isa = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";
>   			clocks = <&clkcfg CLK_CPU>;
>   			tlb-split;
>   			next-level-cache = <&cctrllr>;
> @@ -132,6 +144,9 @@ cpu4: cpu at 4 {
>   			mmu-type = "riscv,sv39";
>   			reg = <4>;
>   			riscv,isa = "rv64imafdc";
> +			riscv,base-isa = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";
>   			clocks = <&clkcfg CLK_CPU>;
>   			tlb-split;
>   			next-level-cache = <&cctrllr>;