[PATCH] riscv: dts: microchip: fix the mpfs' mailbox regs

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

On Tue, 07 Mar 2023 21:10:54 +0000, Conor Dooley wrote:
> The mailbox on PolarFire SoC should really have three reg properties,
> not two. Without splitting into three sections, the system controller's
> QSPI cannot be accessed as it sits inside the current first range. The
> driver & binding have been adapted to account for both two & three
> ranges, so fix the dts too.
> 
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[1/1] riscv: dts: microchip: fix the mpfs' mailbox regs
      https://git.kernel.org/conor/c/e77da13b8e36

Thanks,
Conor.