[PATCH] riscv: dts: microchip: fix the mpfs' mailbox regs

[Palmer Dabbelt]

On Tue, 07 Mar 2023 13:10:54 PST (-0800), Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> The mailbox on PolarFire SoC should really have three reg properties,
> not two. Without splitting into three sections, the system controller's
> QSPI cannot be accessed as it sits inside the current first range. The
> driver & binding have been adapted to account for both two & three
> ranges, so fix the dts too.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index 0a9bb84af438..62b1aec4ffff 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -498,7 +498,8 @@ usb: usb at 20201000 {
>
>  		mbox: mailbox at 37020000 {
>  			compatible = "microchip,mpfs-mailbox";
> -			reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
> +			reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
> +			      <0x0 0x37020800 0x0 0x100>;
>  			interrupt-parent = <&plic>;
>  			interrupts = <96>;
>  			#mbox-cells = <1>;

Acked-by: Palmer Dabbelt <palmer at rivosinc.com>