[PATCH v2 3/3] RISC-V: add T-Head vector errata handling

[Conor Dooley]

On Tue, Jun 27, 2023 at 06:21:14PM +0300, Rémi Denis-Courmont wrote:
> Le perjantaina 23. kesäkuuta 2023, 2.13.05 EEST Heiko Stuebner a écrit :
> > From: Heiko Stuebner <heiko.stuebner at vrull.eu>
> > 
> > T-Head C9xx cores implement an older version (0.7.1) of the vector
> > specification.
> > 
> > Relevant changes concerning the kernel are:
> > - different placement of the SR_VS bit for the vector unit status
> > - different encoding of the vsetvli instruction
> > - different instructions for loads and stores
> > 
> > And a fixed VLEN of 128.
> 
> Ultimately, conformant hardware also has a fixed VLEN of some value.
> 
> So why is that relevant here? is the vlenb CSR not implemented? And even if 
> so, c the value not be retrieved with vsetvli?

I was looking around a bit, and saw a random comment on reddit today
claiming that the c920 has a vlen of 256. Obviously that conflicts with
what is written here, but it is reddit...
Do you know if that is true Heiko, and if it is true, does the c920
populate archid/impid with non-zero values?

Cheers,
Conor.
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