[PATCH v2 3/3] RISC-V: add T-Head vector errata handling

[Rémi Denis-Courmont]

Le perjantaina 23. kesäkuuta 2023, 2.13.05 EEST Heiko Stuebner a écrit :
> From: Heiko Stuebner <heiko.stuebner at vrull.eu>
> 
> T-Head C9xx cores implement an older version (0.7.1) of the vector
> specification.
> 
> Relevant changes concerning the kernel are:
> - different placement of the SR_VS bit for the vector unit status
> - different encoding of the vsetvli instruction
> - different instructions for loads and stores
> 
> And a fixed VLEN of 128.

Ultimately, conformant hardware also has a fixed VLEN of some value.

So why is that relevant here? is the vlenb CSR not implemented? And even if 
so, c the value not be retrieved with vsetvli?

-- 
Rémi Denis-Courmont
http://www.remlab.net/