[PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree

[JeeHeng Sia]

> -----Original Message-----
> From: Conor Dooley <conor.dooley at microchip.com>
> Sent: Monday, December 11, 2023 3:59 PM
> To: JeeHeng Sia <jeeheng.sia at starfivetech.com>
> Cc: Shengyu Qu <wiagn233 at outlook.com>; kernel at esmil.dk; robh+dt at kernel.org; krzysztof.kozlowski+dt at linaro.org;
> krzk at kernel.org; conor+dt at kernel.org; paul.walmsley at sifive.com; palmer at dabbelt.com; aou at eecs.berkeley.edu;
> daniel.lezcano at linaro.org; tglx at linutronix.de; conor at kernel.org; anup at brainfault.org; gregkh at linuxfoundation.org;
> jirislaby at kernel.org; michal.simek at amd.com; Michael Zhu <michael.zhu at starfivetech.com>; drew at beagleboard.org;
> devicetree at vger.kernel.org; linux-riscv at lists.infradead.org; linux-kernel at vger.kernel.org; Leyfoon Tan
> <leyfoon.tan at starfivetech.com>
> Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree
> 
> On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote:
> >
> > > From: Shengyu Qu <wiagn233 at outlook.com>
> > > Sent: Friday, December 8, 2023 8:09 PM
> 
> > > Does the dubhe-80 cores actually support vector? Or vector support
> > >
> > > doesn't exist on actual silicon?
> 
> > We don't have a use case for vector application in JH8100
> 
> I am sorry, but I am not clear on what this means. Do the CPUs on
> the JH8100 support vector or not?
The JH8100 CPU does not support vector operation.