[PATCH v3 2/2] RISC-V: Clean up the Zicbom block size probing

[Heiko Stübner]

Am Dienstag, 6. September 2022, 09:45:09 CEST schrieb Andrew Jones:
> From: Palmer Dabbelt <palmer at rivosinc.com>
> 
> This fixes two issues: I truncated the warning's hart ID when porting to
> the 64-bit hart ID code, and the original code's warning handling could
> fire on an uninitialized hart ID.
> 
> The biggest change here is that riscv_cbom_block_size is no longer
> initialized, as IMO the default isn't sane: there's nothing in the ISA
> that mandates any specific cache block size, so falling back to one will
> just silently produce the wrong answer on some systems.  This also
> changes the probing order so the cache block size is known before
> enabling Zicbom support.
> 
> Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant")
> Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension")
> Reported-by: kernel test robot <lkp at intel.com>
> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> [Rebased on Anup's move patch and applied Conor Dooley's and Heiko
>  Stuebner's changes.]
> Signed-off-by: Andrew Jones <ajones at ventanamicro.com>

Reviewed-by: Heiko Stuebner <heiko at sntech.de>

Retested on Qemu (Zicbom) and D1 (T-Head errata)
Tested-by: Heiko Stuebner <heiko at sntech.de>