[GIT PULL] Microchip DT fixes for v6.0-rc4 (or later)

[Palmer Dabbelt]

On Fri, 02 Sep 2022 09:07:49 PDT (-0700), Conor.Dooley at microchip.com wrote:
> Hey Palmer,
> 
> Two patches here that are really not particularly urgent by themselves.
> Both fix the interrupts dtbs_check warning that I introduced last week.
> 
> As I said on my application mail: "patches for this dt-binding are
> usually merged via the riscv tree so I have taken the liberty of
> bundling it with the dts change".
> I would have sat on this for a little & grouped it with some other
> stuff, but Zong Li wants to do a rename of the binding [0] so to make
> life easier for them (and avoid this change being clobbered...) I
> decided to send this to you this week.
> 
> I did not bother marking it CC: stable since it's just a binding
> checker warning - to be honest, I'd have sent it via for-next if not
> for the fact that the warning fixed by these patches went via fixes
> and I didn't want tooling screaming at me for invalid Fixes: tags..
> 
> If you wish to apply these patches to for-next instead, they are at:
> https://lore.kernel.org/linux-riscv/20220825180417.1259360-1-mail@conchuod.ie/

IMO it's fine to have these on fixes, but it was too late for rc4 -- I'm 
not really sure when the cutoff is, but I generally like to have at 
least an overnight run of the autobuilders (as they find bugs sometimes) and I
try to avoid sending PRs on the weekend unless there's something super pressing
going on.

I've got this on fixes, I'll send them up next week -- probably early, 
as I'll be on a flight on Wednesday night.

Thanks!

> 
> Thanks,
> Conor.
> 
> The following changes since commit 1709c70c31e05e6e87b2ffa0a2b4cc0da4b2c513:
> 
>   Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (2022-08-25 16:38:01 -0700)
> 
> are available in the Git repository at:
> 
>   https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/dt-fixes-for-palmer-6.0-rc4
> 
> for you to fetch changes up to 0dec364ffeb6149aae572ded1e34d4b444c23be6:
> 
>   riscv: dts: microchip: use an mpfs specific l2 compatible (2022-08-31 16:57:51 +0100)
> 
> ----------------------------------------------------------------
> Microchip RISC-V devicetree fixes for 6.0-rc4 (or later)
> 
> A fix for the warnings introduced in rc3 as part of fixing the console
> spam from the L2's isr.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> 
> ----------------------------------------------------------------
> Conor Dooley (2):
>       dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
>       riscv: dts: microchip: use an mpfs specific l2 compatible
> 
>  Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 79 +++++++++++++++++++++++++++++++++++++++++++++++++------------------------------
>  arch/riscv/boot/dts/microchip/mpfs.dtsi                      |  2 +-
>  2 files changed, 50 insertions(+), 31 deletions(-)