[PATCH] riscv: enable software resend of irqs

[Palmer Dabbelt]

On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn at kernel.org wrote:
> Conor Dooley <conor.dooley at microchip.com> writes:
>
>> The PLIC specification does not describe the interrupt pendings bits as
>> read-write, only that they "can be read". To allow for retriggering of
>> interrupts (and the use of the irq debugfs interface) enable
>> HARDIRQS_SW_RESEND for RISC-V.
>>
>> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
>> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
>
> Waking up an old thread. FWIW,
>
> Reviewed-by: Björn Töpel <bjorn at kernel.org>

Thanks.  This look reasonable to me, not sure if the irqchip folks have 
an opinion though?

In theory the PLIC isn't the only interrupt controller (and that spec 
predates most of the implementations), but the SiFive PLIC derived 
interrupt controllers have become a defacto standard and IIRC they're 
the only thing shipping right now so I think it's OK to just stick this 
in arch code.  We could mark it as "if SIFIVE_PLIC" or something, but I 
don't know if that's worth doing.

Either way, this isn't really my thing.  Happy to take it via the RISC-V 
tree, but 

Acked-by: Palmer Dabbelt <palmer at rivosinc.com>
Tested-by: Palmer Dabbelt <palmer at rivosinc.com> # on QEMU

if you want it via the irqchip tree.  I put it over at 
palmer/riscv-irq_sw_resend in case you want to do a shared tree or 
something, but that seems pretty overkill to me here.  It's passing 
all my tests, but that's just QEMU.