[PATCH] riscv: enable software resend of irqs

[Björn Töpel]

Conor Dooley <conor.dooley at microchip.com> writes:

> The PLIC specification does not describe the interrupt pendings bits as
> read-write, only that they "can be read". To allow for retriggering of
> interrupts (and the use of the irq debugfs interface) enable
> HARDIRQS_SW_RESEND for RISC-V.
>
> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Waking up an old thread. FWIW,

Reviewed-by: Björn Töpel <bjorn at kernel.org>