[PATCH v4 2/2] riscv: topology: fix default topology reporting

[Atish Patra]

On Fri, Jul 15, 2022 at 10:53 AM Conor Dooley <mail at conchuod.ie> wrote:
>
> From: Conor Dooley <conor.dooley at microchip.com>
>
> RISC-V has no sane defaults to fall back on where there is no cpu-map
> in the devicetree.
> Without sane defaults, the package, core and thread IDs are all set to
> -1. This causes user-visible inaccuracies for tools like hwloc/lstopo
> which rely on the sysfs cpu topology files to detect a system's
> topology.
>
> On a PolarFire SoC, which should have 4 harts with a thread each,
> lstopo currently reports:
>
> Machine (793MB total)
>   Package L#0
>     NUMANode L#0 (P#0 793MB)
>     Core L#0
>       L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
>       L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
>       L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)
>       L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)
>
> Adding calls to store_cpu_topology() in {boot,smp} hart bringup code
> results in the correct topolgy being reported:
>
> Machine (793MB total)
>   Package L#0
>     NUMANode L#0 (P#0 793MB)
>     L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
>     L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
>     L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
>     L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
>
> CC: stable at vger.kernel.org
> Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
> Reported-by: Brice Goglin <Brice.Goglin at inria.fr>
> Link: https://github.com/open-mpi/hwloc/issues/536
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> Reviewed-by: Sudeep Holla <sudeep.holla at arm.com>
> ---
>  arch/riscv/Kconfig          | 2 +-
>  arch/riscv/kernel/smpboot.c | 3 ++-
>  2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 205c1e2f539c..7ffac8818060 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -52,7 +52,7 @@ config RISCV
>         select COMMON_CLK
>         select CPU_PM if CPU_IDLE
>         select EDAC_SUPPORT
> -       select GENERIC_ARCH_TOPOLOGY if SMP
> +       select GENERIC_ARCH_TOPOLOGY
>         select GENERIC_ATOMIC64 if !64BIT
>         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
>         select GENERIC_EARLY_IOREMAP
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index f1e4948a4b52..b4d5524b1077 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -49,6 +49,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
>         unsigned int curr_cpuid;
>
>         curr_cpuid = smp_processor_id();
> +       store_cpu_topology(curr_cpuid);
>         numa_store_cpu_info(curr_cpuid);
>         numa_add_cpu(curr_cpuid);
>
> @@ -161,9 +162,9 @@ asmlinkage __visible void smp_callin(void)
>         mmgrab(mm);
>         current->active_mm = mm;
>
> +       store_cpu_topology(curr_cpuid);
>         notify_cpu_starting(curr_cpuid);
>         numa_add_cpu(curr_cpuid);
> -       update_siblings_masks(curr_cpuid);
>         set_cpu_online(curr_cpuid, 1);
>
>         /*
> --
> 2.37.1
>

LGTM.
Reviewed-by: Atish Patra <atishp at rivosinc.com>
-- 
Regards,
Atish