[PATCH V3 0/5] Support for 64bit hartid on RV64 platforms

[Palmer Dabbelt]

On Thu, 26 May 2022 22:17:38 PDT (-0700), sunilvl at ventanamicro.com wrote:
> The hartid can be a 64bit value on RV64 platforms. This series updates
> the code so that 64bit hartid can be supported on RV64 platforms.
>
> The series has been tested on both RV32 and RV64 qemu platforms.
>
> Changes since V2:
> 	1) Modified commit messages to mention RV64 and add RB tags.
>
> Changes since V1:
> 	1) Updated RB tag for PATCH 1 and PATCH3
> 	2) Type Casting NR_CPUS before comparing with hartid in PATCH 2
> 	3) Changed commit message of PATCH 2 to provide details about
> 	   the bug it is fixing.
> 	4) Updated PATCH 5 for unaligned 64bit read
>
>
> Sunil V L (5):
>   riscv: cpu_ops_sbi: Add 64bit hartid support on RV64
>   riscv: spinwait: Fix hartid variable type
>   riscv: smp: Add 64bit hartid support on RV64
>   riscv: cpu: Add 64bit hartid support on RV64
>   riscv/efi_stub: Add 64bit boot-hartid support on RV64
>
>  arch/riscv/include/asm/processor.h        |  4 ++--
>  arch/riscv/include/asm/smp.h              |  4 ++--
>  arch/riscv/kernel/cpu.c                   | 26 +++++++++++++----------
>  arch/riscv/kernel/cpu_ops_sbi.c           |  4 ++--
>  arch/riscv/kernel/cpu_ops_spinwait.c      |  4 ++--
>  arch/riscv/kernel/cpufeature.c            |  6 ++++--
>  arch/riscv/kernel/smp.c                   |  4 ++--
>  arch/riscv/kernel/smpboot.c               |  9 ++++----
>  drivers/clocksource/timer-riscv.c         | 15 +++++++------
>  drivers/firmware/efi/libstub/riscv-stub.c | 13 +++++++++---
>  drivers/irqchip/irq-riscv-intc.c          |  7 +++---
>  drivers/irqchip/irq-sifive-plic.c         |  7 +++---
>  12 files changed, 60 insertions(+), 43 deletions(-)

Thanks, this is on for-next.