[PATCH 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-always-on
Anup Patel
apatel at ventanamicro.com
Mon Jul 18 22:47:28 PDT 2022
We add an optional DT property riscv,timer-always-on which if present
in CPU DT node then CPU timer is always powered-on and never loses
context.
Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..33832b8dfaab 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -78,6 +78,12 @@ properties:
- rv64imac
- rv64imafdc
+ riscv,timer-always-on:
+ type: boolean
+ description:
+ If present, the timer is powered through an always-on power
+ domain, therefore it never loses context.
+
# RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
timebase-frequency: false
--
2.34.1
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