[PATCH] riscv: dts: microchip: hook up the mpfs' l2cache

[Palmer Dabbelt]

On Wed, 29 Jun 2022 13:07:33 PDT (-0700), conor at kernel.org wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
>
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")

I just noticed this as I was looking over the PR I just sent, but since 
you're sending PRs I'm no longer re-writing your commits and thus I 
won't be adding stable CCs.  If you want stuff CC'd to stable you'll 
have to either add it to the tags in the commit, or do so after the 
fact.

> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index 3095d08453a1..496d3b7642bd 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -50,6 +50,7 @@ cpu1: cpu at 1 {
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
>
>  			cpu1_intc: interrupt-controller {
> @@ -77,6 +78,7 @@ cpu2: cpu at 2 {
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
>
>  			cpu2_intc: interrupt-controller {
> @@ -104,6 +106,7 @@ cpu3: cpu at 3 {
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
>
>  			cpu3_intc: interrupt-controller {
> @@ -131,6 +134,7 @@ cpu4: cpu at 4 {
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
>  			cpu4_intc: interrupt-controller {
>  				#interrupt-cells = <1>;