[PATCH v2 0/1] Add Polarfire SoC GPIO support
lewis.hanly at microchip.com
lewis.hanly at microchip.com
Wed Jul 13 03:59:09 PDT 2022
From: Lewis Hanly <lewis.hanly at microchip.com>
Add a driver to support the Polarfire SoC gpio controller.
Tested with 5.19-rc5
MPFS gpio interrupts can be configured as direct or
non direct connections to the PLIC (Platform Level Interrupt Controller).
GPIO_INTERRUPT_FAB_CR(31:0) system register will enable GPIO2(31:0)
corresponding interrupt on PLIC. e.g. If GPIO_INTERRUPT_FAB_CR bit0 is set
then GPIO2 bit0 interrupt is available on the direct input pin on the PLIC.
Changes in v2:
Use raw_spinlock.
Use __assign_bit() to assign bit, added a bool variable for value.
Remove unnecessary checking gpio_index.
Remove default from switch statement.
Use const for irq_chip, name updated and use mask/unmask.
Use latest kernel api irq set_chip.
Implemented hierarchical interrupt chip support, although
suggested to use chained interrupt flow I believe this fits better.
Lewis Hanly (1):
gpio: mpfs: add polarfire soc gpio support
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-mpfs.c | 379 +++++++++++++++++++++++++++++++++++++++
3 files changed, 389 insertions(+)
create mode 100644 drivers/gpio/gpio-mpfs.c
--
2.25.1
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