[RFC 1/2] dt-bindings: riscv: document the sifive e24
Conor Dooley
mail at conchuod.ie
Sun Jul 10 04:13:29 PDT 2022
From: Conor Dooley <conor.dooley at microchip.com>
The SiFive E24 is a 32 bit monitor core present on the JH7100.
Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..195e762094a8 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -29,6 +29,7 @@ properties:
- enum:
- sifive,rocket0
- sifive,bullet0
+ - sifive,e24
- sifive,e5
- sifive,e7
- sifive,e71
@@ -75,6 +76,7 @@ properties:
lowercase to simplify parsing.
$ref: "/schemas/types.yaml#/definitions/string"
enum:
+ - rv32imafc
- rv64imac
- rv64imafdc
--
2.37.0
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