[RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h
Guo Ren
guoren at kernel.org
Thu Jul 7 23:10:59 PDT 2022
Sorry all, I forgot this part. If you want to try, please care:
diff --git a/arch/riscv/include/asm/errata_list.h
b/arch/riscv/include/asm/errata_list.h
index 47175d91773d..b252068bfd3a 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -46,7 +46,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma",
SIFIVE_VENDOR_ID, \
* _val is marked as "will be overwritten", so need to set it to 0
* in the default case.
*/
-#define ALT_SVPBMT_SHIFT 61
+#define ALT_SVPBMT_SHIFT (__riscv_xlen-3)
#ifdef CONFIG_ERRATA_THEAD_PBMT
#define ALT_THEAD_PBMT_SHIFT 59
On Tue, Jul 5, 2022 at 6:05 PM <guoren at kernel.org> wrote:
>
> From: Guo Ren <guoren at linux.alibaba.com>
>
> This patch is preparation for rv32 svpbmt, which only moves the svpbmt
> bits definitions into the standard header and no other functionality
> modification. Here is the list of modification:
> - Change u64 to ulong of riscv_page_nocache/mtmask/io functions
> - Using __riscv_xlen instead of 64
>
> Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren at kernel.org>
> ---
> arch/riscv/include/asm/pgtable-32.h | 16 --------
> arch/riscv/include/asm/pgtable-64.h | 55 ---------------------------
> arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++
> arch/riscv/include/asm/pgtable.h | 5 +++
> 4 files changed, 58 insertions(+), 71 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> index 59ba1fbaf784..63b023bd4845 100644
> --- a/arch/riscv/include/asm/pgtable-32.h
> +++ b/arch/riscv/include/asm/pgtable-32.h
> @@ -7,8 +7,6 @@
> #define _ASM_RISCV_PGTABLE_32_H
>
> #include <asm-generic/pgtable-nopmd.h>
> -#include <linux/bits.h>
> -#include <linux/const.h>
>
> /* Size of region mapped by a page global directory */
> #define PGDIR_SHIFT 22
> @@ -17,20 +15,6 @@
>
> #define MAX_POSSIBLE_PHYSMEM_BITS 34
>
> -/*
> - * rv32 PTE format:
> - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> - * PFN reserved for SW D A G U X W R V
> - */
> #define _PAGE_PFN_MASK GENMASK(31, 10)
>
> -#define _PAGE_NOCACHE 0
> -#define _PAGE_IO 0
> -#define _PAGE_MTMASK 0
> -
> -/* Set of bits to preserve across pte_modify() */
> -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> - _PAGE_WRITE | _PAGE_EXEC | \
> - _PAGE_USER | _PAGE_GLOBAL))
> -
> #endif /* _ASM_RISCV_PGTABLE_32_H */
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 5c2aba5efbd0..3263b910e7d2 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -6,10 +6,6 @@
> #ifndef _ASM_RISCV_PGTABLE_64_H
> #define _ASM_RISCV_PGTABLE_64_H
>
> -#include <linux/bits.h>
> -#include <linux/const.h>
> -#include <asm/errata_list.h>
> -
> extern bool pgtable_l4_enabled;
> extern bool pgtable_l5_enabled;
>
> @@ -67,25 +63,8 @@ typedef struct {
>
> #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))
>
> -/*
> - * rv64 PTE format:
> - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> - * N MT RSV PFN reserved for SW D A G U X W R V
> - */
> #define _PAGE_PFN_MASK GENMASK(53, 10)
>
> -/*
> - * [62:61] Svpbmt Memory Type definitions:
> - *
> - * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> - * 11 - Rsvd Reserved for future standard use
> - */
> -#define _PAGE_NOCACHE_SVPBMT (1UL << 61)
> -#define _PAGE_IO_SVPBMT (1UL << 62)
> -#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> -
> /*
> * [63:59] T-Head Memory Type definitions:
> *
> @@ -98,40 +77,6 @@ typedef struct {
> #define _PAGE_IO_THEAD (1UL << 63)
> #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>
> -static inline u64 riscv_page_mtmask(void)
> -{
> - u64 val;
> -
> - ALT_SVPBMT(val, _PAGE_MTMASK);
> - return val;
> -}
> -
> -static inline u64 riscv_page_nocache(void)
> -{
> - u64 val;
> -
> - ALT_SVPBMT(val, _PAGE_NOCACHE);
> - return val;
> -}
> -
> -static inline u64 riscv_page_io(void)
> -{
> - u64 val;
> -
> - ALT_SVPBMT(val, _PAGE_IO);
> - return val;
> -}
> -
> -#define _PAGE_NOCACHE riscv_page_nocache()
> -#define _PAGE_IO riscv_page_io()
> -#define _PAGE_MTMASK riscv_page_mtmask()
> -
> -/* Set of bits to preserve across pte_modify() */
> -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> - _PAGE_WRITE | _PAGE_EXEC | \
> - _PAGE_USER | _PAGE_GLOBAL | \
> - _PAGE_MTMASK))
> -
> static inline int pud_present(pud_t pud)
> {
> return (pud_val(pud) & _PAGE_PRESENT);
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index b9e13a8fe2b7..414a0a919ef0 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -6,6 +6,11 @@
> #ifndef _ASM_RISCV_PGTABLE_BITS_H
> #define _ASM_RISCV_PGTABLE_BITS_H
>
> +/*
> + * PTE format:
> + * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> + * N MT[2] RSV & PFN reserved for SW D A G U X W R V
> + */
> #define _PAGE_ACCESSED_OFFSET 6
>
> #define _PAGE_PRESENT (1 << 0)
> @@ -18,6 +23,54 @@
> #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
> #define _PAGE_SOFT (1 << 8) /* Reserved for software */
>
> +#ifndef __ASSEMBLY__
> +/*
> + * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions:
> + *
> + * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> + * 11 - Rsvd Reserved for future standard use
> + */
> +#define _PAGE_NOCACHE_SVPBMT (1UL << (__riscv_xlen-3))
> +#define _PAGE_IO_SVPBMT (1UL << (__riscv_xlen-2))
> +#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> +
> +static inline ulong riscv_page_mtmask(void)
> +{
> + ulong val;
> +
> + ALT_SVPBMT(val, _PAGE_MTMASK);
> + return val;
> +}
> +
> +static inline ulong riscv_page_nocache(void)
> +{
> + ulong val;
> +
> + ALT_SVPBMT(val, _PAGE_NOCACHE);
> + return val;
> +}
> +
> +static inline ulong riscv_page_io(void)
> +{
> + ulong val;
> +
> + ALT_SVPBMT(val, _PAGE_IO);
> + return val;
> +}
> +
> +#define _PAGE_NOCACHE riscv_page_nocache()
> +#define _PAGE_IO riscv_page_io()
> +#define _PAGE_MTMASK riscv_page_mtmask()
> +
> +/* Set of bits to preserve across pte_modify() */
> +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> + _PAGE_WRITE | _PAGE_EXEC | \
> + _PAGE_USER | _PAGE_GLOBAL | \
> + _PAGE_MTMASK))
> +#endif
> +
> #define _PAGE_SPECIAL _PAGE_SOFT
> #define _PAGE_TABLE _PAGE_PRESENT
>
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index edc68759b69d..5d5ba6513c14 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -8,7 +8,12 @@
>
> #include <linux/mmzone.h>
> #include <linux/sizes.h>
> +#ifndef __ASSEMBLY__
> +#include <linux/bits.h>
> +#include <linux/const.h>
>
> +#include <asm/errata_list.h>
> +#endif
> #include <asm/pgtable-bits.h>
>
> #ifndef CONFIG_MMU
> --
> 2.36.1
>
--
Best Regards
Guo Ren
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