[PATCH v2] riscv: dts: starfive: correct number of external interrupts

[Conor.Dooley at microchip.com]

On 07/07/2022 19:55, Mark Kettenis wrote:
> The PLIC integrated on the Vic_U7_Core integrated on the StarFive
> JH7100 SoC actually supports 133 external interrupts.  127 of these
> are exposed to the outside world; the remainder are used by other
> devices that are part of the core-complex such as the L2 cache
> controller.  But all 133 interrupts are external interrupts as far
> as the PLIC is concerned.  Fix the property so that the driver can
> manage these additional interrupts, which is important since the
> interrupts for the L2 cache controller are enabled by default.

The missing 4 for the l2cache controller certainly make sense &
the documentation does mention there being interrupts as far up
as 131 in Table 28.
Table 33 disagrees and has an interrupt 133.
God knows what those two are used for, but the documentation
certainly makes it look like they do exist.

Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/vic_u7_manual_with_creativecommons.pdf # Page 44 & 45
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

> 
> Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree")
> Signed-off-by: Mark Kettenis <kettenis at openbsd.org>
> ---
> 
> ChangeLog:
> 
> v2: - Fix commit message
> 
> 
>  arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index 69f22f9aad9d..f48e232a72a7 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -118,7 +118,7 @@ plic: interrupt-controller at c000000 {
>  			interrupt-controller;
>  			#address-cells = <0>;
>  			#interrupt-cells = <1>;
> -			riscv,ndev = <127>;
> +			riscv,ndev = <133>;
>  		};
>  
>  		clkgen: clock-controller at 11800000 {