[PATCH v6 3/4] riscv: Add support for non-coherent devices using zicbom extension

[Guo Ren]

On Thu, Jul 7, 2022 at 7:03 AM Heiko Stübner <heiko at sntech.de> wrote:
>
> Hi Guo,
>
> Am Mittwoch, 6. Juli 2022, 01:32:12 CEST schrieb Guo Ren:
> > On Wed, Jul 6, 2022 at 6:47 AM Heiko Stuebner <heiko at sntech.de> wrote:
> > >
> > > The Zicbom ISA-extension was ratified in november 2021
> > > and introduces instructions for dcache invalidate, clean
> > > and flush operations.
> > >
> > > Implement cache management operations for non-coherent devices
> > > based on them.
> > >
> > > Of course not all cores will support this, so implement an
> > > alternative-based mechanism that replaces empty instructions
> > > with ones done around Zicbom instructions.
> > >
> > > As discussed in previous versions, assume the platform
> > > being coherent by default so that non-coherent devices need
> > > to get marked accordingly by firmware.
> > >
> > > Reviewed-by: Christoph Hellwig <hch at lst.de>
> > > Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> > > Cc: Christoph Hellwig <hch at lst.de>
> > > Cc: Atish Patra <atish.patra at wdc.com>
> > > Cc: Guo Ren <guoren at kernel.org>
> > > Cc: Anup Patel <anup at brainfault.org>
> > > ---
> > >  arch/riscv/Kconfig                   |  31 ++++++++
> > >  arch/riscv/Makefile                  |   4 +
> > >  arch/riscv/include/asm/cache.h       |   4 +
> > >  arch/riscv/include/asm/cacheflush.h  |  10 +++
> > >  arch/riscv/include/asm/errata_list.h |  19 ++++-
> > >  arch/riscv/include/asm/hwcap.h       |   1 +
> > >  arch/riscv/kernel/cpu.c              |   1 +
> > >  arch/riscv/kernel/cpufeature.c       |  24 ++++++
> > >  arch/riscv/kernel/setup.c            |   2 +
> > >  arch/riscv/mm/Makefile               |   1 +
> > >  arch/riscv/mm/dma-noncoherent.c      | 112 +++++++++++++++++++++++++++
> > >  11 files changed, 208 insertions(+), 1 deletion(-)
> > >  create mode 100644 arch/riscv/mm/dma-noncoherent.c
> > >
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 32ffef9f6e5b..f7b2b3a4b7f1 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -113,6 +113,7 @@ config RISCV
> > >         select MODULES_USE_ELF_RELA if MODULES
> > >         select MODULE_SECTIONS if MODULES
> > >         select OF
> > > +       select OF_DMA_DEFAULT_COHERENT
> > >         select OF_EARLY_FLATTREE
> > >         select OF_IRQ
> > >         select PCI_DOMAINS_GENERIC if PCI
> > > @@ -218,6 +219,14 @@ config PGTABLE_LEVELS
> > >  config LOCKDEP_SUPPORT
> > >         def_bool y
> > >
> > > +config RISCV_DMA_NONCOHERENT
> > > +       bool
> > > +       select ARCH_HAS_DMA_PREP_COHERENT
> > > +       select ARCH_HAS_SYNC_DMA_FOR_DEVICE
> > > +       select ARCH_HAS_SYNC_DMA_FOR_CPU
> > > +       select ARCH_HAS_SETUP_DMA_OPS
> > > +       select DMA_DIRECT_REMAP
> > > +
> > >  source "arch/riscv/Kconfig.socs"
> > >  source "arch/riscv/Kconfig.erratas"
> > >
> > > @@ -376,6 +385,28 @@ config RISCV_ISA_SVPBMT
> > >
> > >            If you don't know what to do here, say Y.
> > >
> > > +config CC_HAS_ZICBOM
> > > +       bool
> > > +       default y if 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicbom)
> > > +       default y if 32BIT && $(cc-option,-mabi=lp64 -march=rv32ima_zicbom)
> >
> > -mabi=lp64 for rv32?
>
> Thanks for catching that! :-)
Okay, Add my "Reviewed-by: Guo Ren <guoren at kernel.org>" in your next version.

>
> When I converted over to using the real instructions for Zicbom instead of
> pre-coded ones, I used a different format first for detecting the Zicbom
> existence and I guess when moving over to the above I made a mistake
> in the conversion.
>
> In any case, that should of course be ilp32, same as in the Makefile.
> With updated opensbi and Qemu I have now re-tested all possible
> combinations and am pretty hopefully that this should fit now.
>
> v7 following shortly.
>
> Thanks
> Heiko
>
>


-- 
Best Regards
 Guo Ren