[PATCH 0/5] RISC-V: Add cpu-map topology information nodes

[Sudeep Holla]

On Tue, Jul 05, 2022 at 08:33:39PM +0000, Conor.Dooley at microchip.com wrote:
> 
> 
> On 05/07/2022 21:19, Sudeep Holla wrote:
> > On Tue, Jul 05, 2022 at 08:04:31PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley at microchip.com>
> >>
> >> It was reported to me that the Hive Unmatched incorrectly reports
> >> its topology to hwloc, but the StarFive VisionFive did in [0] &
> >> a subsequent off-list email from Brice (the hwloc maintainer).
> >> This turned out not to be entirely true, the /downstream/ version
> >> of the VisionFive does work correctly but not upstream, as the
> >> downstream devicetree has a cpu-map node that was added recently.
> >>
> >> This series adds a cpu-map node to all upstream devicetrees, which
> >> I have tested on mpfs & fu540. The first patch is lifted directly
> >> from the downstream StarFive devicetree.
> >>
> > 
> > Reviewed-by: Sudeep Holla <sudeep.holla at arm.com>
> > 
> > I would recommend to have sane defaults in core risc-v code in case of
> > absence of /cpu-map node as it is optional. The reason I mentioned is that
> > Conor mentioned how the default values in absence of the node looked quite
> > wrong. I don't know if it is possible on RISC-V but on ARM64 we do have
> > default values if arch_topology fails to set based on DT/ACPI.
> > 
> 
> Yeah the defaults are all -1. I'll add some sane defaults for a v2.

Sorry I didn't mean it to be part of this series. This series of DT changes
are just fine on their own.

-- 
Regards,
Sudeep