[PATCH] riscv: dts: microchip: hook up the mpfs's l2cache

[Daire McNamara]

Reviewed-by: Daire McNamara <daire.mcnamara at microchip.com>

> From: Conor Dooley <conor.dooley at microchip.com>
> Date: Monday, 4 July 2022 at 10:04
> To: FPGA ESS Linux patches <FPGA-ESS-Linux-Patches at microchip.com>
> Cc: Conor Dooley - M52691 <Conor.Dooley at microchip.com>
> Subject: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache
> 
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
> 
> Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
> Reviewed-by: Sudeep Holla <sudeep.holla at arm.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index ed8739350587..2df555a57003 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -50,6 +50,7 @@ cpu1: cpu at 1 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>  
>                          cpu1_intc: interrupt-controller {
> @@ -77,6 +78,7 @@ cpu2: cpu at 2 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>  
>                          cpu2_intc: interrupt-controller {
> @@ -104,6 +106,7 @@ cpu3: cpu at 3 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>  
>                          cpu3_intc: interrupt-controller {
> @@ -131,6 +134,7 @@ cpu4: cpu at 4 {
>                          riscv,isa = "rv64imafdc";
>                          clocks = <&clkcfg CLK_CPU>;
>                          tlb-split;
> +                       next-level-cache = <&cctrllr>;
>                          status = "okay";
>                          cpu4_intc: interrupt-controller {
>                                  #interrupt-cells = <1>;
> -- 
> 2.36.1