[PATCH V7] irqchip/sifive-plic: Fixup EOI failed when masked

[Marc Zyngier]

On 2021-11-07 13:09, Guo Ren wrote:
> On Sat, Nov 6, 2021 at 9:45 PM Anup Patel <anup at brainfault.org> wrote:
>> 
>> On Fri, Nov 5, 2021 at 3:18 PM <guoren at kernel.org> wrote:
>> >
>> > From: Guo Ren <guoren at linux.alibaba.com>
>> >
>> > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the driver,
>> > only the first interrupt could be handled, and continue irq is blocked by
>> > hw. Because the riscv plic couldn't complete masked irq source which has
>> > been disabled in enable register. The bug was firstly reported in [1].
>> >
>> > Here is the description of Interrupt Completion in PLIC spec [2]:
>> >
>> > The PLIC signals it has completed executing an interrupt handler by
>> > writing the interrupt ID it received from the claim to the claim/complete
>> > register. The PLIC does not check whether the completion ID is the same
>> > as the last claim ID for that target. If the completion ID does not match
>> > an interrupt source that is currently enabled for the target, the
>> >                          ^^ ^^^^^^^^^ ^^^^^^^
>> > completion is silently ignored.
>> >
>> > [1] http://lists.infradead.org/pipermail/linux-riscv/2021-July/007441.html
>> > [2] https://github.com/riscv/riscv-plic-spec/blob/8bc15a35d07c9edf7b5d23fec9728302595ffc4d/riscv-plic.adoc
>> >
>> > Fixes: bb0fed1c60cc ("irqchip/sifive-plic: Switch to fasteoi flow")
>> > Reported-by: Vincent Pelletier <plr.vincent at gmail.com>
>> > Tested-by: Nikita Shubin <nikita.shubin at maquefel.me>
>> > Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
>> 
>> Looks good to me.
>> 
>> Reviewed-by: Anup Patel <anup at brainfault.org>
> Thx
> 
> @Marc Zyngier
> Could you help to take the patch into your tree include "Anup's
> Reviewed-by"? Or Let me update a new version of the patch.

You should have received [1], which shows you what I have done.

         M.

[1] 
https://lore.kernel.org/all/163620881803.626.5045336370262044443.tip-bot2@tip-bot2/
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