[PATCH v19 01/17] clk: Add RISC-V Canaan Kendryte K210 clock driver

Damien Le Moal Damien.LeMoal at wdc.com
Wed Feb 10 21:41:45 EST 2021

On 2021/02/11 11:34, Stephen Boyd wrote:
> Quoting Damien Le Moal (2021-02-09 21:02:14)
>> Add a clock provider driver for the Canaan Kendryte K210 RISC-V SoC.
>> This new driver with the compatible string "canaan,k210-clk" implements
>> support for the full clock structure of the K210 SoC. Since it is
>> required for the correct operation of the SoC, this driver is
>> selected by default for compilation when the SOC_CANAAN option is
>> selected.
>> With this change, the k210-sysctl driver is turned into a simple
>> platform driver which enables its power bus clock and triggers
>> populating its child nodes. The sysctl driver retains the SOC early
>> initialization code, but the implementation now relies on the new
>> function k210_clk_early_init() provided by the new clk-k210 driver.
>> The clock structure implemented and many of the coding ideas for the
>> driver come from the work by Sean Anderson on the K210 support for the
>> U-Boot project.
>> Cc: Stephen Boyd <sboyd at kernel.org>
>> Cc: Michael Turquette <mturquette at baylibre.com>
>> Cc: linux-clk at vger.kernel.org
>> Signed-off-by: Damien Le Moal <damien.lemoal at wdc.com>
>> ---
> No change log :/

It is in the cover letter :)

> Minor nitpicks but otherwise
> Reviewed-by: Stephen Boyd <sboyd at kernel.org>

Thanks !

I will address your nits in follow up patches. I really want to get this queued
in 5.12. So not resending a v20 :)

Damien Le Moal
Western Digital Research

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