[PATCH AUTOSEL 4.19 8/8] riscv, entry: fix misaligned base for excp_vect_table
Sasha Levin
sashal at kernel.org
Mon Apr 5 17:05:15 BST 2021
From: Zihao Yu <yuzihao at ict.ac.cn>
[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]
In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.
Signed-off-by: Zihao Yu <yuzihao at ict.ac.cn>
Reviewed-by: Anup Patel <anup at brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt at google.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---
arch/riscv/kernel/entry.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index a03821b2656a..d9de22686e27 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -449,6 +449,7 @@ ENDPROC(__fstate_restore)
.section ".rodata"
+ .align LGREG
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned
--
2.30.2
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