[PATCH AUTOSEL 5.4 12/13] riscv, entry: fix misaligned base for excp_vect_table

Sasha Levin sashal at kernel.org
Mon Apr 5 17:04:57 BST 2021

From: Zihao Yu <yuzihao at ict.ac.cn>

[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao at ict.ac.cn>
Reviewed-by: Anup Patel <anup at brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt at google.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
 arch/riscv/kernel/entry.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 8ca479831142..9c87ae77ad5d 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -387,6 +387,7 @@ ENTRY(__switch_to)
 	.section ".rodata"
+	.align LGREG
 	/* Exception vector table */
 	RISCV_PTR do_trap_insn_misaligned

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