[PATCH] riscv: Fix Kendryte K210 device tree

[Damien Le Moal]

The Kendryte K210 SoC CLINT is compatible with Sifive clint v0
(sifive,clint0). Fix the Kendryte K210 device tree clint entry to be
inline with the sifive timer definition documented in
Documentation/devicetree/bindings/timer/sifive,clint.yaml. Rename the
clint0 entry to "timer", fix the register mapping and fix the interrupt
extended entry.

This fixes boot failures with Kendryte K210 SoC boards.

Signed-off-by: Damien Le Moal <damien.lemoal at wdc.com>
---
 arch/riscv/boot/dts/kendryte/k210.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/kendryte/k210.dtsi b/arch/riscv/boot/dts/kendryte/k210.dtsi
index c1df56ccb8d5..48d65fea45e9 100644
--- a/arch/riscv/boot/dts/kendryte/k210.dtsi
+++ b/arch/riscv/boot/dts/kendryte/k210.dtsi
@@ -95,10 +95,11 @@ sysctl: sysctl at 50440000 {
 			#clock-cells = <1>;
 		};
 
-		clint0: interrupt-controller at 2000000 {
+		timer at 2000000 {
 			compatible = "riscv,clint0";
-			reg = <0x2000000 0xC000>;
-			interrupts-extended = <&cpu0_intc 3>,  <&cpu1_intc 3>;
+			reg = <0x2000000 0x10000>;
+			interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7
+						&cpu1_intc 3 &cpu1_intc 7>;
 			clocks = <&sysctl K210_CLK_ACLK>;
 		};
 
-- 
2.26.2