[PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align with HPG

[sashiko-bot at kernel.org]

> HPG requires the controller/PHY GDSCs powered up and all controller/PHY
> clocks enabled first, then the controller's reset and the PHY's reset
> toggled together as a group, PARF_DEVICE_TYPE set right after, and the
> rest of the PARF/DBI config left until the PHY is ready.
> 
> Make use of phy_init() and phy_reset(), and change the call flow to:
> 
>   qcom_pcie_host_init():
>     phy_init()             (PHY GDSCs/regulators/clocks up)
>     qcom_pcie_ops::init:
>       enable controller clocks
>       assert controller reset
>       phy_reset()           (toggle the PHY's own reset)
>       deassert controller reset
>       write PARF_DEVICE_TYPE
> [ ... ]
> site into qcom_pcie_host_init()/qcom_pcie_host_deinit() keeps them at the
> same point relative to that platform's own clock/reset programming, so its
> init sequence doesn't change either.
> 
> Signed-off-by: Qiang Yu <qiang.yu at oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com?part=1