[PATCH v5 04/11] phy: qualcomm: qmp-combo: Ignore Type-C orientation for Glymur DP mode

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] phy: qualcomm: incomplete orientation override breaks DP in reverse mode
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commit 23ac8c6629ba34694c05a91c6de05d93bd4e6b04
Author: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>

phy: qualcomm: qmp-combo: Ignore Type-C orientation for Glymur DP mode

Glymur platforms use a fixed DP lane mapping and do not support DP PHY mode
reversal based on Type-C orientation. Add a configuration flag to ignore
reverse orientation during DP mode setup and enable it for Glymur, ensuring
that QSERDES_DP_PHY_MODE is always programmed with the fix mode value (0x5c).

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index b672adb33fc5b..646e97a528863 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

[ ... ]

> @@ -3570,6 +3575,7 @@ static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
>  static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
>  {
>  	bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
> +	const struct qmp_phy_cfg *cfg = qmp->cfg;
>  	const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
>  	u32 val;
>  
> @@ -3583,7 +3589,7 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
>  
>  	writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
>  
> -	if (reverse)
> +	if (reverse && !cfg->dp_mode_ignore_reverse)
>  		writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
>  	else
>  		writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);

[Severity: High]
Does this orientation override fully handle reverse mode on Glymur platforms?

In drivers/phy/qualcomm/phy-qcom-qmp-combo.c, within
qmp_combo_configure_dp_mode(), the reverse variable still dynamically
swaps the powered-down lanes prior to this check:

	if (dp_opts->lanes == 4 || reverse)
		val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
	if (dp_opts->lanes == 4 || !reverse)
		val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;

If the platform has fixed DP lane mapping and ignores orientation, won't
this incorrectly power off the active lanes when a Type-C cable is
inserted in the reverse orientation?

Additionally, qmp_v8_configure_dp_phy() also appears to bypass the
intended fixed configuration forced by dp_mode_ignore_reverse, as the
lane driver and transceiver bias enable values still dynamically swap
based on orientation:

	if (dp_opts->lanes == 1) {
		bias0_en = reverse ? 0x3e : 0x15;
		bias1_en = reverse ? 0x15 : 0x3e;
		drvr0_en = reverse ? 0x13 : 0x10;
		drvr1_en = reverse ? 0x10 : 0x13;

Could these omissions cause DisplayPort output over Type-C to completely
fail when the cable is inserted in the reverse orientation, as the PHY
configuration will incorrectly power down the active DP lanes and apply
wrong transceiver bias settings?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com?part=4