[PATCH v23 05/15] media: dt-bindings: Add CAMSS device for Kaanapali
Hangxiang Ma
hangxiang.ma at oss.qualcomm.com
Mon Nov 2 01:14:04 PST 2026
On 10/31/2026 7:52 PM, Vladimir Zapolskiy wrote:
> On 10/28/26 17:20, Hangxiang Ma wrote:
>> Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Kaanapali
>> platform.
>>
>> The Kaanapali platform provides:
>> - 6 x CSIPHY (CSI Physical Layer)
>> - 3 x TPG (Test Pattern Generator)
>> - 3 x CSID (CSI Decoder)
>> - 2 x CSID Lite
>> - 3 x VFE (Video Front End), 5 RDI per VFE
>> - 2 x VFE Lite, 4 RDI per VFE Lite
>>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue at linaro.org>
>> Reviewed-by: Rob Herring (Arm) <robh at kernel.org>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma at oss.qualcomm.com>
>> ---
>> .../bindings/media/qcom,kaanapali-camss.yaml | 306 +++++++++++
>> ++++++++++
>> 1 file changed, 306 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-
>> camss.yaml b/Documentation/devicetree/bindings/media/qcom,kaanapali-
>> camss.yaml
>> new file mode 100644
>> index 000000000000..dec451fc940f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml
>> @@ -0,0 +1,306 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Kaanapali Camera Subsystem (CAMSS)
>> +
>> +maintainers:
>> + - Hangxiang Ma <hangxiang.ma at oss.qualcomm.com>
>> +
>> +description:
>> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,kaanapali-camss
>> +
>> + reg:
>> + maxItems: 14
>> +
>> + reg-names:
>> + items:
>> + - const: top
>> + - const: csid0
>> + - const: csid1
>> + - const: csid2
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: csitpg0
>> + - const: csitpg1
>> + - const: csitpg2
>
> Rename it to 'tpgX'.
>
ACK
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe2
>> + - const: vfe_lite0
>> + - const: vfe_lite1
>> +
>> + clocks:
>> + maxItems: 23
>> +
>> + clock-names:
>> + items:
>> + - const: camnoc_nrt_axi
>> + - const: camnoc_rt_axi
>> + - const: cpas_ahb
>> + - const: cpas_fast_ahb
>> + - const: cpas_vfe0
>> + - const: cpas_vfe1
>> + - const: cpas_vfe2
>> + - const: cpas_vfe_lite
>> + - const: csid
>> + - const: csid_csiphy_rx
>
> The common name is 'csiphy_rx', the clock supplies CSIPHYs and non-CSID
> TPGs.
ACK
>
>> + - const: gcc_axi_hf
>> + - const: gcc_axi_sf
>
> Unused clock.
ACK
>
>> + - const: vfe0
>> + - const: vfe0_fast_ahb
>> + - const: vfe1
>> + - const: vfe1_fast_ahb
>> + - const: vfe2
>> + - const: vfe2_fast_ahb
>> + - const: vfe_lite
>> + - const: vfe_lite_ahb
>> + - const: vfe_lite_cphy_rx
>> + - const: vfe_lite_csid
>> + - const: qdss_debug_xo
>> +
>> + interrupts:
>> + maxItems: 10
>> +
>> + interrupt-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid2
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe2
>> + - const: vfe_lite0
>> + - const: vfe_lite1
>> +
>> + interconnects:
>> + maxItems: 2
>> +
>> + interconnect-names:
>> + items:
>> + - const: ahb
>> + - const: hf_mnoc
>> +
>> + iommus:
>> + items:
>> + - description: S1 HLOS IFE non-protected stream
>> +
>> + power-domains:
>> + items:
>> + - description: IFE0 GDSC - Global Distributed Switch Controller
>> for IFE0.
>> + - description: IFE1 GDSC - Global Distributed Switch Controller
>> for IFE1.
>> + - description: IFE2 GDSC - Global Distributed Switch Controller
>> for IFE2.
>> + - description: Titan Top GDSC - Titan ISP Block, Global
>> Distributed Switch Controller.
>> +
>> + power-domain-names:
>> + items:
>> + - const: ife0
>> + - const: ife1
>> + - const: ife2
>> + - const: top
>> +
>> + ports:
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + description:
>> + CSI input ports. Each port receives the CSI data
>> + decoded by the matching CSIPHY.
>> +
>> + patternProperties:
>> + "^port@[0-5]$":
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + Input port for receiving CSI data from CSIPHY 0-5.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + bus-type:
>> + enum:
>> + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
>> + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
>> +
>> + required:
>> + - data-lanes
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - interrupt-names
>> + - interconnects
>> + - interconnect-names
>> + - iommus
>> + - power-domains
>> + - power-domain-names
>> + - ports
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
>> + #include <dt-bindings/clock/qcom,kaanapali-camcc.h>
>> + #include <dt-bindings/interconnect/qcom,icc.h>
>> + #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/qcom,rpmhpd.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + isp at 900b000 {
>> + compatible = "qcom,kaanapali-camss";
>> +
>> + reg = <0x0 0x0900b000 0x0 0x1000>,
>> + <0x0 0x09253000 0x0 0x5e80>,
>> + <0x0 0x09263000 0x0 0x5e80>,
>> + <0x0 0x09273000 0x0 0x5e80>,
>> + <0x0 0x092d3000 0x0 0x3880>,
>> + <0x0 0x092e7000 0x0 0x3880>,
>> + <0x0 0x093fd000 0x0 0x400>,
>> + <0x0 0x093fe000 0x0 0x400>,
>> + <0x0 0x093ff000 0x0 0x400>,
>> + <0x0 0x09151000 0x0 0x20000>,
>> + <0x0 0x09171000 0x0 0x20000>,
>> + <0x0 0x09191000 0x0 0x20000>,
>> + <0x0 0x092dc000 0x0 0x1300>,
>> + <0x0 0x092f0000 0x0 0x1300>;
>> +
>> + reg-names = "top",
>> + "csid0",
>> + "csid1",
>> + "csid2",
>> + "csid_lite0",
>> + "csid_lite1",
>> + "csitpg0",
>> + "csitpg1",
>> + "csitpg2",
>> + "vfe0",
>> + "vfe1",
>> + "vfe2",
>> + "vfe_lite0",
>> + "vfe_lite1";
>> +
>> + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
>> + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
>> + <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
>> + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
>> + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
>> + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
>> + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
>> + <&camcc CAM_CC_CSID_CLK>,
>> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
>> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
>> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
>> + <&camcc CAM_CC_TFE_0_MAIN_CLK>,
>> + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_TFE_1_MAIN_CLK>,
>> + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_TFE_2_MAIN_CLK>,
>> + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
>> + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
>> +
>> + clock-names = "camnoc_nrt_axi",
>> + "camnoc_rt_axi",
>> + "cpas_ahb",
>> + "cpas_fast_ahb",
>> + "cpas_vfe0",
>> + "cpas_vfe1",
>> + "cpas_vfe2",
>> + "cpas_vfe_lite",
>> + "csid",
>> + "csid_csiphy_rx",
>> + "gcc_axi_hf",
>> + "gcc_axi_sf",
>> + "vfe0",
>> + "vfe0_fast_ahb",
>> + "vfe1",
>> + "vfe1_fast_ahb",
>> + "vfe2",
>> + "vfe2_fast_ahb",
>> + "vfe_lite",
>> + "vfe_lite_ahb",
>> + "vfe_lite_cphy_rx",
>> + "vfe_lite_csid",
>> + "qdss_debug_xo";
>> +
>> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
>> +
>> + interrupt-names = "csid0",
>> + "csid1",
>> + "csid2",
>> + "csid_lite0",
>> + "csid_lite1",
>> + "vfe0",
>> + "vfe1",
>> + "vfe2",
>> + "vfe_lite0",
>> + "vfe_lite1";
>> +
>> + interconnects = <&gem_noc MASTER_APPSS_PROC
>> QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_CAMERA_CFG
>> QCOM_ICC_TAG_ACTIVE_ONLY>,
>> + <&mmss_noc MASTER_CAMNOC_HF
>> QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "ahb",
>> + "hf_mnoc";
>> +
>> + iommus = <&apps_smmu 0x1c00 0x00>;
>> +
>> + power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
>> + <&camcc CAM_CC_TFE_1_GDSC>,
>> + <&camcc CAM_CC_TFE_2_GDSC>,
>> + <&camcc CAM_CC_TITAN_TOP_GDSC>;
>> + power-domain-names = "ife0",
>> + "ife1",
>> + "ife2",
>> + "top";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port at 0 {
>> + reg = <0>;
>> + camss_csiphy0_ep: endpoint {
>> + data-lanes = <1 2 3 4>;
>> + remote-endpoint = <&csiphy0_out>;
>> + };
>> + };
>> + };
>> + };
>> + };
>>
>
> In general it looks good.
>
---
Best Regrads,
Hangxiang
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