[PATCH v2 2/2] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.

[Vinod Koul]

On 04-04-26, 18:49, Caleb James DeLisle wrote:
> Introduce support for EcoNet PCIe PHY controllers found in EN751221
> and EN7528 SoCs, these SoCs are not identical but are similar, each
> having one Gen1 port, and one Gen1/Gen2 port.
> 
> Co-developed-by: Ahmed Naseef <naseefkm at gmail.com>
> Signed-off-by: Ahmed Naseef <naseefkm at gmail.com>
> [cjd at cjdns.fr: add EN751221 support and refactor for clarity]
> Signed-off-by: Caleb James DeLisle <cjd at cjdns.fr>
> ---
>  MAINTAINERS                   |   1 +
>  drivers/phy/Kconfig           |  12 +++
>  drivers/phy/Makefile          |   1 +
>  drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++++++++++++++++++
>  4 files changed, 194 insertions(+)
>  create mode 100644 drivers/phy/phy-econet-pcie.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1b016212e4cb..b2d37c7c80af 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9177,6 +9177,7 @@ M:	Caleb James DeLisle <cjd at cjdns.fr>
>  L:	linux-mips at vger.kernel.org
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
> +F:	drivers/phy/phy-econet-pcie.c
>  
>  ECRYPT FILE SYSTEM
>  M:	Tyler Hicks <code at tyhicks.com>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 227b9a4c612e..9aad68829d72 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -66,6 +66,18 @@ config PHY_CAN_TRANSCEIVER
>  	  functional modes using gpios and sets the attribute max link
>  	  rate, for CAN drivers.
>  
> +config PHY_ECONET_PCIE
> +	tristate "EcoNet PCIe-PHY Driver"
> +	depends on ECONET || COMPILE_TEST
> +	depends on OF
> +	select GENERIC_PHY
> +	select REGMAP_MMIO
> +	help
> +	  Say Y here to add support for EcoNet PCIe PHY driver.
> +	  This driver create the basic PHY instance and provides initialize
> +	  callback for PCIe GEN1 and GEN2 ports. This PHY is found on
> +	  EcoNet SoCs including EN751221 and EN7528.
> +
>  config PHY_GOOGLE_USB
>  	tristate "Google Tensor SoC USB PHY driver"
>  	select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index f49d83f00a3d..42959ed383fd 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
>  obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)	+= phy-core-mipi-dphy.o
>  obj-$(CONFIG_PHY_AIROHA_PCIE)		+= phy-airoha-pcie.o
>  obj-$(CONFIG_PHY_CAN_TRANSCEIVER)	+= phy-can-transceiver.o
> +obj-$(CONFIG_PHY_ECONET_PCIE)		+= phy-econet-pcie.o
>  obj-$(CONFIG_PHY_GOOGLE_USB)		+= phy-google-usb.o
>  obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
>  obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o
> diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c
> new file mode 100644
> index 000000000000..d2c6e0c1f331
> --- /dev/null
> +++ b/drivers/phy/phy-econet-pcie.c
> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Author: Caleb James DeLisle <cjd at cjdns.fr>
> + *	   Ahmed Naseef <naseefkm at gmail.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +/* Rx detection timing for EN751221: 16*8 clock cycles  */
> +#define EN751221_RXDET_VAL		16
> +
> +/* Rx detection timing when in power mode 3 */
> +#define EN75_RXDET_P3_REG		0xa28
> +#define EN75_RXDET_P3_MASK		GENMASK(17, 9)
> +
> +/* Rx detection timing when in power mode 2 */
> +#define EN75_RXDET_P2_REG		0xa2c
> +#define EN75_RXDET_P2_MASK		GENMASK(8, 0)
> +
> +/* Rx impedance */
> +#define EN75_RX_IMPEDANCE_REG		0xb2c
> +#define EN75_RX_IMPEDANCE_MASK		GENMASK(13, 12)
> +enum en75_rx_impedance {
> +	EN75_RX_IMPEDANCE_100_OHM	= 0,
> +	EN75_RX_IMPEDANCE_95_OHM	= 1,
> +	EN75_RX_IMPEDANCE_90_OHM	= 2,
> +};
> +
> +/* PLL Invert clock */
> +#define EN75_PLL_PH_INV_REG		0x4a0
> +#define EN75_PLL_PH_INV_MASK		BIT(5)
> +
> +struct en75_phy_op {
> +	u32 reg;
> +	u32 mask;
> +	u32 val;
> +};
> +
> +struct en7528_pcie_phy {
> +	struct regmap *regmap;
> +	const struct en75_phy_op *data;
> +};
> +
> +/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */
> +static const struct en75_phy_op en7528_phy_gen1[] = {
> +	{
> +		.reg = EN75_PLL_PH_INV_REG,
> +		.mask = EN75_PLL_PH_INV_MASK,
> +		.val = 1,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */
> +static const struct en75_phy_op en7528_phy_gen2[] = {
> +	{
> +		.reg = EN75_RX_IMPEDANCE_REG,
> +		.mask = EN75_RX_IMPEDANCE_MASK,
> +		.val = EN75_RX_IMPEDANCE_95_OHM,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */
> +static const struct en75_phy_op en751221_phy_gen2[] = {
> +	{
> +		.reg = EN75_RXDET_P3_REG,
> +		.mask = EN75_RXDET_P3_MASK,
> +		.val = EN751221_RXDET_VAL,
> +	},
> +	{
> +		.reg = EN75_RXDET_P2_REG,
> +		.mask = EN75_RXDET_P2_MASK,
> +		.val = EN751221_RXDET_VAL,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +static int en75_pcie_phy_init(struct phy *phy)
> +{
> +	struct en7528_pcie_phy *ephy = phy_get_drvdata(phy);
> +	const struct en75_phy_op *data = ephy->data;
> +	int i, ret;
> +	u32 val;
> +
> +	for (i = 0; data[i].mask || data[i].val; i++) {
> +		if (i)
> +			usleep_range(1000, 2000);
> +
> +		val = field_prep(data[i].mask, data[i].val);

Please see:

https://sashiko.dev/#/patchset/20260425173642.406089-1-cjd%40cjdns.fr

-- 
~Vinod