[PATCH 1/2] phy: zynqmp: fix clock error handling in xpsgtr_phy_init()
Michal Simek
michal.simek at amd.com
Mon Jul 20 22:39:03 PDT 2026
On 7/20/26 17:38, Radhey Shyam Pandey wrote:
> Propagate clk_prepare_enable() failures to the caller instead of
> returning success, and disable the reference clock on initialization
> error paths to avoid leaking clock references when phy_exit() is not
> called.
>
> Fixes: 25d700833513 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save")
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
> ---
> drivers/phy/xilinx/phy-zynqmp.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqmp.c
> index fe6b4925d166..c8230f2bda62 100644
> --- a/drivers/phy/xilinx/phy-zynqmp.c
> +++ b/drivers/phy/xilinx/phy-zynqmp.c
> @@ -658,12 +658,13 @@ static int xpsgtr_phy_init(struct phy *phy)
> {
> struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
> struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
> - int ret = 0;
> + int ret;
>
> mutex_lock(>r_dev->gtr_mutex);
>
> /* Configure and enable the clock when peripheral phy_init call */
> - if (clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk]))
> + ret = clk_prepare_enable(gtr_dev->clk[gtr_phy->refclk]);
> + if (ret)
> goto out;
>
> /* Skip initialization if not required. */
> @@ -673,7 +674,7 @@ static int xpsgtr_phy_init(struct phy *phy)
> if (gtr_dev->tx_term_fix) {
> ret = xpsgtr_phy_tx_term_fix(gtr_phy);
> if (ret < 0)
> - goto out;
> + goto out_disable_clk;
>
> gtr_dev->tx_term_fix = false;
> }
> @@ -687,7 +688,7 @@ static int xpsgtr_phy_init(struct phy *phy)
> */
> ret = xpsgtr_configure_pll(gtr_phy);
> if (ret)
> - goto out;
> + goto out_disable_clk;
>
> xpsgtr_lane_set_protocol(gtr_phy);
>
> @@ -705,6 +706,10 @@ static int xpsgtr_phy_init(struct phy *phy)
> break;
> }
>
> + goto out;
> +
> +out_disable_clk:
> + clk_disable_unprepare(gtr_dev->clk[gtr_phy->refclk]);
> out:
> mutex_unlock(>r_dev->gtr_mutex);
> return ret;
Reviewed-by: Michal Simek <michal.simek at amd.com>
Thanks,
Michal
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