[PATCH v5 02/10] dt-bindings: phy: qcom,qmp-usb: Add Glymur USB UNI PHY compatible

[Krzysztof Kozlowski]

On 17/10/2025 02:15, Wesley Cheng wrote:
>>> Technically its all handling the same clock branch (CXO), we have the
>>> TCSR clkref register that allows us to gate the CXO to the USB PHY, as
>>
>>
>> Ah, exactly. Then clkref is not a clock. You need rather proper clock
>> hierarchy.
>>
>>> CXO is shared across several HW blocks, so it allows us to properly
>>> powerdown the PHY even though other clients are voting for CXO on.  Then
>>> we obviously have to remove our vote to the overall CXO, so that it can
>>> potentially be shutdown.
>>>
>>> Maybe we can rename it to "clkref" for the CXO handle and
>>> "clkref_switch" for the TCSRCC handle?
>>
>> Naming is better, but it is still not correct. This is not independent
>> clock signal. It is the same clock.
>>
> 
> Hmmm... I guess that's why I kept the same clkref tag, to denote that 
> its the same clock, but one is a switch/gate for it.  Would you happen 
> to have any suggestions you might have that makes it clearer for 
> everyone to understand?
To me it looks like:

|-----|            |-----------|           |------------------|
|clock|------------|TCSRCC gate|-----------|clkref to this dev|
|-----|            |-----------|           |------------------|

So you need proper clock controller for TCSR (TCSR Clock Controller, in
short TCSRCC, what a surprise!) which will take input, add gate and
produce clock for this device.

Nothing non-standard, all Qualcomm SoCs have it, every other platform
has it in some way.


Best regards,
Krzysztof