[PATCH v4 2/4] dt-bindings: PCI: qcom: Document the Glymur PCIe Controller

[Abel Vesa]

On 25-10-14 18:50:37, Qiang Yu wrote:
> On Sun, Oct 12, 2025 at 05:01:45AM +0200, Krzysztof Kozlowski wrote:
> > On 11/10/2025 14:15, Abel Vesa wrote:
> > >>  
> > >>  properties:
> > >>    compatible:
> > >> -    const: qcom,pcie-x1e80100
> > >> +    oneOf:
> > >> +      - const: qcom,pcie-x1e80100
> > >> +      - items:
> > >> +          - enum:
> > >> +              - qcom,glymur-pcie
> > >> +          - const: qcom,pcie-x1e80100
> > >>  
> > > 
> > > The cnoc_sf_axi clock is not found on Glymur, at least according to this:
> > > 
> > > https://lore.kernel.org/all/20250925-v3_glymur_introduction-v1-19-24b601bbecc0@oss.qualcomm.com/
> > > 
> > > And dtbs_check reports the following:
> > > 
> > > arch/arm64/boot/dts/qcom/glymur-crd.dtb: pci at 1b40000 (qcom,glymur-pcie): clock-names: ['aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'noc_aggr'] is too short
> > >         from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
> > > 
> > > One more thing:
> > > 
> > > arch/arm64/boot/dts/qcom/glymur-crd.dtb: pci at 1b40000 (qcom,glymur-pcie): max-link-speed: 5 is not one of [1, 2, 3, 4]
> > >         from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
> > > 
> > 
> > So that's another Glymur patch which wasn't ever tested?
> 
> I tested all of these patch and also did dtb checks. That's how I found
> cnoc_sf_axi clock is not required. There was a discussion about whether we
> need to limit max speed to 16 GT and I limited it. I may forget to do dtb
> checks again after changing it to 32 GT. Let me push another patch to fix
> this.

Still, you need to add glymur specific clocks entry then, to fix the schema
w.r.t cnoc_sf_axi not being needed.


Best regards,
Abel