[PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required

[Geraldo Nascimento]

On Mon, Jun 30, 2025 at 11:33:19PM +0200, Heiko Stübner wrote:
> Am Montag, 30. Juni 2025, 20:22:01 Mitteleuropäische Sommerzeit schrieb Geraldo Nascimento:
> > Current code enables only Lane 0 because pwr_cnt will be incremented on
> > first call to the function. Let's reorder the enablement code to enable
> > all 4 lanes through GRF.
> > 
> > Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
> > Reviewed-by: Robin Murphy <robin.murphy at arm.com>
> > 
> > Signed-off-by: Valmantas Paliksa <walmis at gmail.com>
> > Signed-off-by: Geraldo Nascimento <geraldogabriel at gmail.com>
> 
> hmm, if Valmantas is the original author you should probably keep that authorship
>   git commit --amend --author="Valmantas Paliksa <walmis at gmail.com>"
> should do the trick.
> 
> The first signed-off should be from the patch author, then your signed-off
> indicates you handling the patch later as part of this series.
> 
> [or, if you modified the code of the patch heavily, Co-developed-by could
>  also be appropriate]
> 

Hi Heiko,

thanks for the pointer on doing things right. I'd hate to appropriate
someone's else work. I already emailed Valmantas and he's fine with
the inclusion of his signed-off, so let's give him due credit.

Geraldo Nascimento

> Heiko