[PATCH] phy: qcom-qmp-ufs: Fix HS-G4 PHY init table for sc7280

[Xilin Wu]

On 2025/7/5 21:06:56, Dmitry Baryshkov wrote:
> On Fri, Jun 13, 2025 at 10:41:48PM +0800, Xilin Wu wrote:
>> The PHY is limited to operating in HS-G3 mode during the initial PCS
>> registers initialization. Extra PHY init sequence is required to allow
>> HS-G4 mode to work when needed.
> 
> I can't find corresponding settings in either of HPGs.
> 

I believe there was a mistake when initially adding support for sc7280 
UFS PHY based on downstream code. In downstream [1] the 
HSGEAR_CAPABILITY registers are programmed to 0x3 **only** when Gear 4 
is not needed, while the current upstream driver always writes to this 
register regardless of the UFS Gear. [2]

I don't have access to the HPGs. The Gear4 specific init sequence is 
found in the Qualcomm proprietary UEFI driver code.

[1]:https://github.com/NothingOSS/android_kernel_msm-5.4_nothing_sm7325/blob/sm7325/s/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-yupik.h#L355

[2]: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c#n215

>>
>> Fixes: 8abe9792d1ff ("phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280")
>> Signed-off-by: Xilin Wu <sophon at radxa.com>
>> ---
>> This might need testing on sm8150, sm8250 and sc8180x as well.
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index b33e2e2b5014d3ca8f19b623ba080887f53e616d..7797be329d75f95c80863e05351d0cf55fdf38c2 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -570,6 +570,13 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
>>   
>>   static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
>>   	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x0b),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x2d),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xb0),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xff),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x1b),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>> +	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>>   	QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
>>   };
>>   
>>
>> ---
>> base-commit: bc6e0ba6c9bafa6241b05524b9829808056ac4ad
>> change-id: 20250613-sc7280-ufsphy-g4-fix-024542f31fac
>>
>> Best regards,
>> -- 
>> Xilin Wu <sophon at radxa.com>
>>
> 


-- 
Best regards,
Xilin Wu <sophon at radxa.com>