[PATCH v4 5/5] phy: qcom: qmp-pcie: add QMP PCIe PHY tables for Kaanapali

[Dmitry Baryshkov]

On Mon, Nov 24, 2025 at 02:24:38AM -0800, Qiang Yu wrote:
> Add QMP PCIe PHY support for the Kaanapali platform.
> 
> Signed-off-by: Jingyi Wang <jingyi.wang at oss.qualcomm.com>
> Reviewed-by: Abel Vesa <abel.vesa at linaro.org>
> Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
> Signed-off-by: Qiang Yu <qiang.yu at oss.qualcomm.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 194 +++++++++++++++++++++++++++++++
>  1 file changed, 194 insertions(+)
> 
> @@ -3363,6 +3516,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
>  	.ln_shrd	= 0x8000,
>  };
>  
> +static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_0 = {

Is it really 8.0 or 8.20?

> +	.serdes		= 0x1000,
> +	.pcs		= 0x1400,
> +	.pcs_misc	= 0x1800,
> +	.tx		= 0x0000,
> +	.rx		= 0x0200,
> +	.tx2		= 0x0800,
> +	.rx2		= 0x0a00,
> +};
> +
>  static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = {
>  	.serdes     = 0x8000,
>  	.pcs        = 0x9000,
> @@ -4425,6 +4588,34 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
>  	.phy_status             = PHYSTATUS_4_20,
>  };
>  
> +static const struct qmp_phy_cfg qmp_v8_gen3x2_pciephy_cfg = {
> +	.lanes = 2,
> +
> +	.offsets		= &qmp_pcie_offsets_v8_0,
> +
> +	.tbls = {
> +		.serdes			= kaanapali_qmp_gen3x2_pcie_serdes_tbl,
> +		.serdes_num		= ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_serdes_tbl),
> +		.tx			= kaanapali_qmp_gen3x2_pcie_tx_tbl,
> +		.tx_num			= ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_tx_tbl),
> +		.rx			= kaanapali_qmp_gen3x2_pcie_rx_tbl,
> +		.rx_num			= ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_rx_tbl),
> +		.pcs			= kaanapali_qmp_gen3x2_pcie_pcs_tbl,
> +		.pcs_num		= ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_pcs_tbl),
> +		.pcs_misc		= kaanapali_qmp_gen3x2_pcie_pcs_misc_tbl,
> +		.pcs_misc_num		= ARRAY_SIZE(kaanapali_qmp_gen3x2_pcie_pcs_misc_tbl),
> +	},
> +
> +	.reset_list		= sdm845_pciephy_reset_l,
> +	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),
> +	.vreg_list		= qmp_phy_vreg_l,
> +	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
> +	.regs			= pciephy_v8_regs_layout,
> +
> +	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
> +	.phy_status		= PHYSTATUS_4_20,
> +};
> +
>  static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {
>  	.lanes = 4,
>  
> @@ -5209,6 +5400,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
>  	}, {
>  		.compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
>  		.data = &ipq9574_gen3x2_pciephy_cfg,
> +	}, {
> +		.compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy",
> +		.data = &qmp_v8_gen3x2_pciephy_cfg,
>  	}, {
>  		.compatible = "qcom,msm8998-qmp-pcie-phy",
>  		.data = &msm8998_pciephy_cfg,
> 
> -- 
> 2.34.1
> 
> 
> -- 
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-- 
With best wishes
Dmitry