[PATCH 1/2] phy: qcom: qmp-pcie: Update PHY settings for SA8775P

[Konrad Dybcio]

On 4/23/25 1:15 PM, Mrinmay Sarkar wrote:
> This change updates the PHY settings to align with the latest
> PCIe PHY Hardware Programming Guide for both PCIe controllers
> on the SA8775P platform.
> 
> Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar at oss.qualcomm.com>
> ---

Please also mention that these updates happen to solve the stability
issues seen with Gen4 speeds

[...]

>  static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
> @@ -3398,8 +3402,8 @@ static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
>  		.tx_num		= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
>  		.rx		= qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
>  		.rx_num		= ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
> -		.pcs		= sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
> -		.pcs_num		= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
> +		.pcs		= sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
> +		.pcs_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
>  		.pcs_misc		= sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
>  		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
>  	},

So QCS8300 and SA8775 are closely related - since you're making updates
for both, please also mention this in the commit message and describe
the impact it has (e.g. that it fixes electrical settings for both platforms
that largely re-use an IP block)

Konrad