[PATCH v4 3/6] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3

[Johan Hovold]

On Wed, Sep 25, 2024 at 11:38:46AM +0800, Qiang Yu wrote:
> 
> On 9/24/2024 11:15 PM, Johan Hovold wrote:
> > On Tue, Sep 24, 2024 at 03:14:41AM -0700, Qiang Yu wrote:
> > > Currently driver supports only x4 lane based functionality using tx/rx and
> > > tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3,
> > > PCIe3 related QMP PHY provides additional programming which are available
> > > as txz and rxz based register set. Hence adds txz and rxz based registers
> > > usage and programming sequences.
> > > Phy register setting for txz and rxz will
> > > be applied to all 8 lanes. Some lanes may have different settings on
> > > several registers than txz/rxz, these registers should be programmed after
> > > txz/rxz programming sequences completing.

> > Please expand and clarify what you mean by this.

> PCIe3 supports 8 lanes, so in general, we have to program 8 pairs tx/rx
> registers. However, most of tx/rx registers of different lanes have
> same settings, so the configuration for all 8 lanes tx/rx registers is
> a little repetitive.
> 
> Hence, txz/rxz registers are included. The values programmed into txz/rxz
> registers by software will be "broadcasted" to all 8 lanes by hardware.
> Some lanes may have different settings on several registers than txz/rxz.
> In order to ensure the different values take effect, they need to be
> programmed after txz/rxz programming sequences completing.

Thanks for clarifying. This is how I interpreted it, but please include
(some or all of of) what you just wrote to make this more clear in the
commit message.

Johan