[PATCH V6 5/5] phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries
Adam Ford
aford173 at gmail.com
Wed Sep 4 16:30:33 PDT 2024
The lookup table contains entries which use the integer divider
instead of just the fractional divider. Since the set and round
functions check both the integer divider values and the LUT values,
it's no longer necessary to keep the integer divider values in the
lookup table, as can be dynamically calcuated.
Signed-off-by: Adam Ford <aford173 at gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf at kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf at kontron.de>
---
V6: Fix typos in commit message
V5: No Change
V4: New to series
---
drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 83 +++-----------------
1 file changed, 13 insertions(+), 70 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
index 9a21dbbf1a82..1203143bad7a 100644
--- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
@@ -69,25 +69,16 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 23750000,
.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
- }, {
- .pixclk = 24000000,
- .pll_div_regs = { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 },
}, {
.pixclk = 24024000,
.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
}, {
.pixclk = 25175000,
.pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
- }, {
- .pixclk = 25200000,
- .pll_div_regs = { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 26750000,
.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
- }, {
- .pixclk = 27000000,
- .pll_div_regs = { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 27027000,
.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
}, {
@@ -105,18 +96,9 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 35000000,
.pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
- }, {
- .pixclk = 36000000,
- .pll_div_regs = { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 36036000,
.pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
- }, {
- .pixclk = 40000000,
- .pll_div_regs = { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 },
- }, {
- .pixclk = 43200000,
- .pll_div_regs = { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 },
}, {
.pixclk = 43243200,
.pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
@@ -132,19 +114,13 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 50349650,
.pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
- }, {
- .pixclk = 50400000,
- .pll_div_regs = { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 },
}, {
.pixclk = 53250000,
.pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
}, {
.pixclk = 53500000,
.pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
- }, {
- .pixclk = 54000000,
- .pll_div_regs = { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 54054000,
.pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
}, {
@@ -153,10 +129,7 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 59340659,
.pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
- }, {
- .pixclk = 59400000,
- .pll_div_regs = { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 61500000,
.pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
}, {
@@ -168,10 +141,7 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 70000000,
.pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },
- }, {
- .pixclk = 72000000,
- .pll_div_regs = { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 72072000,
.pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },
}, {
@@ -183,10 +153,7 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 78500000,
.pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
- }, {
- .pixclk = 80000000,
- .pll_div_regs = { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 82000000,
.pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },
}, {
@@ -213,10 +180,7 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 100699300,
.pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },
- }, {
- .pixclk = 100800000,
- .pll_div_regs = { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 102500000,
.pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
}, {
@@ -228,19 +192,13 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 107000000,
.pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
- }, {
- .pixclk = 108000000,
- .pll_div_regs = { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 108108000,
.pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
}, {
.pixclk = 118000000,
.pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },
- }, {
- .pixclk = 118800000,
- .pll_div_regs = { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 123000000,
.pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },
}, {
@@ -261,10 +219,7 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 140000000,
.pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },
- }, {
- .pixclk = 144000000,
- .pll_div_regs = { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 148352000,
.pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },
}, {
@@ -288,9 +243,6 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 165000000,
.pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },
- }, {
- .pixclk = 180000000,
- .pll_div_regs = { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 },
}, {
.pixclk = 185625000,
.pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },
@@ -309,25 +261,16 @@ static const struct phy_config phy_pll_cfg[] = {
}, {
.pixclk = 213000000,
.pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },
- }, {
- .pixclk = 216000000,
- .pll_div_regs = { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 },
}, {
.pixclk = 216216000,
.pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },
- }, {
- .pixclk = 237600000,
- .pll_div_regs = { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 254000000,
.pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },
}, {
.pixclk = 277500000,
.pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
- }, {
- .pixclk = 288000000,
- .pll_div_regs = { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 },
- }, {
+ }, {
.pixclk = 297000000,
.pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
},
--
2.43.0
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