[PATCH v3] phy: cadence: Sierra: Add single link SGMII register configuration

[Roger Quadros]

On 22/05/2023 20:24, Marcin Wierzbicki wrote:
> Add single link SGMII register configuration for no SSC for
> cdns,sierra-phy-t0 compatibility string.
> The configuration is based on Sierra Programmer's Guide and
> validated in Cisco CrayAR SoC.
> 
> Co-developed-by: Bartosz Wawrzyniak <bwawrzyn at cisco.com>
> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn at cisco.com>
> Signed-off-by: Marcin Wierzbicki <mawierzb at cisco.com>
> ---
> v3> - all reported comments were addressed

:)
You should summarize what changes were done.

> - v2: https://lore.kernel.org/lkml/20230508160142.2489365-1-mawierzb@cisco.com/T/#u
> 
> v2
> - rebased version on top of commit 0cfa43ab46b5 ("phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration")
> - v1: https://lore.kernel.org/lkml/20230419093008.195094-1-mawierzb@cisco.com/T/
> 
> Regards,
> Marcin

Reviewed-by: Roger Quadros <rogerq at kernel.org>

-- 
cheers,
-roger