[PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

[Swapnil Kashinath Jakhade]

Hi Vinod,

> -----Original Message-----
> From: Roger Quadros <rogerq at kernel.org>
> Sent: Monday, February 20, 2023 9:50 PM
> To: Swapnil Kashinath Jakhade <sjakhade at cadence.com>;
> vkoul at kernel.org; kishon at kernel.org; linux-phy at lists.infradead.org; linux-
> kernel at vger.kernel.org
> Cc: Milind Parab <mparab at cadence.com>
> Subject: Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
> configuration
> 
> EXTERNAL MAIL
> 
> 
> 
> 
> On 20/02/2023 16:12, Swapnil Jakhade wrote:
> > Add register sequences for PCIe + SGMII PHY multilink configuration.
> > This has been validated on TI J7 platforms.
> >
> > Signed-off-by: Swapnil Jakhade <sjakhade at cadence.com>
> 
> Reviewed-by: Roger Quadros <rogerq at kernel.org>

Could you please consider reviewing and merging this patch.

Thanks & regards,
Swapnil