[PATCH v2 08/13] ARM: dts: qcom: sdx55: List the property values vertically

[Konrad Dybcio]

On 24.02.2023 11:59, Manivannan Sadhasivam wrote:
> To align with the rest of the devicetree files and the relative properties,
> let's list the values of properties such as {reg/clock/interrupt}-names
> vertically.
> 
> Suggested-by: Konrad Dybcio <konrad.dybcio at linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio at linaro.org>

Konrad
>  arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++-----
>  1 file changed, 18 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
> index b411c4ae34c3..61fdd601fc26 100644
> --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
> @@ -393,7 +393,11 @@ pcie_ep: pcie-ep at 1c00000 {
>  			      <0x40001000 0x1000>,
>  			      <0x40200000 0x100000>,
>  			      <0x01c03000 0x3000>;
> -			reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> +			reg-names = "parf",
> +				    "dbi",
> +				    "elbi",
> +				    "atu",
> +				    "addr_space",
>  				    "mmio";
>  
>  			qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> @@ -405,12 +409,18 @@ pcie_ep: pcie-ep at 1c00000 {
>  				 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
>  				 <&gcc GCC_PCIE_SLEEP_CLK>,
>  				 <&gcc GCC_PCIE_0_CLKREF_CLK>;
> -			clock-names = "aux", "cfg", "bus_master", "bus_slave",
> -				      "slave_q2a", "sleep", "ref";
> +			clock-names = "aux",
> +				      "cfg",
> +				      "bus_master",
> +				      "bus_slave",
> +				      "slave_q2a",
> +				      "sleep",
> +				      "ref";
>  
>  			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
>  				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "global", "doorbell";
> +			interrupt-names = "global",
> +					  "doorbell";
>  			reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
>  			wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
>  			resets = <&gcc GCC_PCIE_BCR>;
> @@ -434,7 +444,10 @@ pcie_phy: phy at 1c07000 {
>  				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
>  				 <&gcc GCC_PCIE_0_CLKREF_CLK>,
>  				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> -			clock-names = "aux", "cfg_ahb", "ref", "refgen";
> +			clock-names = "aux",
> +				      "cfg_ahb",
> +				      "ref",
> +				      "refgen";
>  
>  			resets = <&gcc GCC_PCIE_PHY_BCR>;
>  			reset-names = "phy";