[PATCH 4/5] arm64: dts: qcom: ipq5018: Add USB related nodes
Nitheesh Sekar
quic_nsekar at quicinc.com
Wed Aug 30 19:50:32 PDT 2023
On 8/31/2023 1:45 AM, Dmitry Baryshkov wrote:
> On Fri, 25 Aug 2023 at 12:37, Nitheesh Sekar <quic_nsekar at quicinc.com> wrote:
>> Add USB phy and controller nodes.
>>
>> Co-developed-by: Amandeep Singh <quic_amansing at quicinc.com>
>> Signed-off-by: Amandeep Singh <quic_amansing at quicinc.com>
>> Signed-off-by: Nitheesh Sekar <quic_nsekar at quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
>> 1 file changed, 54 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 9f13d2dcdfd5..ff477923a823 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -238,6 +238,60 @@
>> status = "disabled";
>> };
>> };
>> +
>> + usbphy0: phy at 5b000 {
>> + compatible = "qcom,ipq5018-usb-hsphy";
>> + reg = <0x0005b000 0x120>;
>> +
>> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
>> +
>> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
>> +
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + usb: usb2 at 8a00000 {
>> + compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
>> + reg = <0x08af8800 0x400>;
>> +
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hs_phy_irq";
>> +
>> + clocks = <&gcc GCC_USB0_MASTER_CLK>,
>> + <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
>> + <&gcc GCC_USB0_SLEEP_CLK>,
>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> + clock-names = "core",
>> + "iface",
>> + "sleep",
>> + "mock_utmi";
>> +
>> + resets = <&gcc GCC_USB0_BCR>;
>> +
>> + qcom,select-utmi-as-pipe-clk;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + status = "disabled";
>> +
>> + usb2_0_dwc: usb at 8a00000 {
> Could you please remove the `2_0' part of the label?
Sure.
Regards,
Nitheesh
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