[PATCH v8 9/9] [DO NOT MERGE] arm64: dts: ls1088ardb: Add serdes bindings
Sean Anderson
sean.anderson at seco.com
Thu Oct 27 12:11:13 PDT 2022
This adds serdes support to the LS1088ARDB. I have tested the QSGMII
ports as well as the two 10G ports. The SFP slot is now fully supported,
instead of being modeled as a fixed-link.
Linux hangs around when the serdes is initialized if the si5341 is
enabled with the in-tree driver, so I have modeled it as a two fixed
clocks instead. There are a few registers in the QIXIS FPGA which
control the SFP GPIOs; I have modeled them as discrete GPIO controllers
for now. I never saw the AQR105 interrupt fire; not sure what was going
on, but I have removed it to force polling.
The MC firmware needs to be fairly new (it must support
DPAA2_MAC_FEATURE_PROTOCOL_CHANGE), and the DPC needs to set the macs to
MAC_LINK_TYPE_BACKPLANE. This will break ethernet if those features are
not enabled. I am not sure what the upstreaming plan should be.
Signed-off-by: Sean Anderson <sean.anderson at seco.com>
---
Changes in v8:
- Rename serdes phy handles like the LS1046A
- Add SFP slot binding
- Fix incorrect lane ordering (it's backwards on the LS1088A just like it is in
the LS1046A).
- Fix duplicated lane 2 (it should have been lane 3).
- Fix incorrectly-documented value for XFI1.
- Remove interrupt for aquantia phy. It never fired for whatever reason,
preventing the link from coming up.
- Add GPIOs for QIXIS FPGA.
- Enable MAC1 PCS
- Remove si5341 binding
Changes in v4:
- Convert to new bindings
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 168 +++++++++++++++++-
1 file changed, 166 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 1bfbce69cc8b..dac3337acbc9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -10,17 +10,143 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
#include "fsl-ls1088a.dtsi"
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+
+ clocks {
+ si5341_xtal: clock-48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+ };
+
+ sfp_slot: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c>;
+ los-gpios = <&los_stat 5 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&los_stat 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&brdcfg9 4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&serdes1 {
+ //clocks = <&si5341 0 8>, <&si5341 0 9>;
+ clocks = <&clk_100mhz>, <&clk_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+
+ /*
+ * XXX: Lane A uses pins SD1_RX3_P/N! That is, the lane numbers and pin
+ * numbers are _reversed_.
+ */
+ serdes1_A: phy at 0 {
+ #phy-cells = <0>;
+ reg = <0>;
+
+ /* QSGb */
+ qsgmii-0 {
+ fsl,pccr = <0x9>;
+ fsl,index = <0>;
+ fsl,cfg = <0x1>;
+ phy-type = <PHY_TYPE_QSGMII>;
+ };
+ };
+
+ serdes1_B: phy at 1 {
+ #phy-cells = <0>;
+ reg = <1>;
+
+ /* QSGa */
+ qsgmii-1 {
+ fsl,pccr = <0x9>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ phy-type = <PHY_TYPE_QSGMII>;
+ };
+ };
+
+ serdes1_C: phy at 2 {
+ #phy-cells = <0>;
+ reg = <2>;
+
+ /* SG1 */
+ sgmii-1 {
+ fsl,pccr = <0x8>;
+ fsl,index = <2>;
+ fsl,cfg = <0x1>;
+ phy-type = <PHY_TYPE_2500BASEX>;
+ };
+
+ /*
+ * XFI1
+ * Table 23-1 and section 23.5.16.4 disagree; this reflects the
+ * table.
+ *
+ * fsl,cfg is documented as 1, but it is set to 2 by the RCW!
+ * This is the same as the LS1046A.
+ */
+ xfi-0 {
+ fsl,pccr = <0xb>;
+ fsl,index = <0>;
+ fsl,cfg = <0x2>;
+ phy-type = <PHY_TYPE_10GBASER>;
+ };
+ };
+
+ serdes1_D: phy at 3 {
+ #phy-cells = <0>;
+ reg = <3>;
+
+ /* SG2 */
+ sgmii-3 {
+ fsl,pccr = <0x8>;
+ fsl,index = <3>;
+ fsl,cfg = <0x1>;
+ phy-type = <PHY_TYPE_2500BASEX>;
+ };
+
+ /* XFI2 */
+ xfi-1 {
+ fsl,pccr = <0xb>;
+ fsl,index = <1>;
+ fsl,cfg = <0x1>;
+ phy-type = <PHY_TYPE_10GBASER>;
+ };
+ };
+};
+
+&dpmac1 {
+ managed = "in-band-status";
+ pcs-handle = <&pcs1>;
+ phys = <&serdes1_C>;
+ sfp = <&sfp_slot>;
};
&dpmac2 {
phy-handle = <&mdio2_aquantia_phy>;
phy-connection-type = "10gbase-r";
+ managed = "in-band-status";
pcs-handle = <&pcs2>;
+ phys = <&serdes1_D>;
};
&dpmac3 {
@@ -28,6 +154,7 @@ &dpmac3 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_0>;
+ phys = <&serdes1_A>;
};
&dpmac4 {
@@ -35,6 +162,7 @@ &dpmac4 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_1>;
+ phys = <&serdes1_A>;
};
&dpmac5 {
@@ -42,6 +170,7 @@ &dpmac5 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_2>;
+ phys = <&serdes1_A>;
};
&dpmac6 {
@@ -49,6 +178,7 @@ &dpmac6 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_3>;
+ phys = <&serdes1_A>;
};
&dpmac7 {
@@ -56,6 +186,7 @@ &dpmac7 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_0>;
+ phys = <&serdes1_B>;
};
&dpmac8 {
@@ -63,6 +194,7 @@ &dpmac8 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_1>;
+ phys = <&serdes1_B>;
};
&dpmac9 {
@@ -70,6 +202,7 @@ &dpmac9 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_2>;
+ phys = <&serdes1_B>;
};
&dpmac10 {
@@ -77,6 +210,7 @@ &dpmac10 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_3>;
+ phys = <&serdes1_B>;
};
&emdio1 {
@@ -128,7 +262,6 @@ &emdio2 {
mdio2_aquantia_phy: ethernet-phy at 0 {
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
reg = <0x0>;
};
};
@@ -171,6 +304,12 @@ rtc at 51 {
interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>;
};
};
+
+ sfp_i2c: i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
};
};
@@ -185,8 +324,29 @@ nand at 0,0 {
};
fpga: board-control at 2,0 {
- compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis",
+ "simple-bus";
reg = <0x2 0x0 0x0000100>;
+ ranges = <0x0 0x2 0x0 0x0000100>;
+
+ los_stat: gpio-controller at 1d {
+ #gpio-cells = <2>;
+ compatible = "fsl,fpga-qixis-los-stat",
+ "ni,169445-nand-gpio";
+ reg = <0x1d 0x1>;
+ reg-names = "dat";
+ no-output;
+ };
+
+ brdcfg9: gpio-controller at 59 {
+ #gpio-cells = <2>;
+ compatible = "fsl,fpga-qixis-brdcfg9",
+ "ni,169445-nand-gpio";
+ reg = <0x59 0x1>;
+ reg-names = "dat";
+ };
};
};
@@ -203,6 +363,10 @@ &esdhc {
status = "okay";
};
+&pcs_mdio1 {
+ status = "okay";
+};
+
&pcs_mdio2 {
status = "okay";
};
--
2.35.1.1320.gc452695387.dirty
More information about the linux-phy
mailing list